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Parallel I/O Ports
7-360
MC68360 USER’S MANUAL
For each DDx bit, the definition is as follows:
0 = General-purpose I/O. The peripheral functions of the pin are not used.
1 = Dedicated peripheral function. The pin is used by the internal module. The
on-chip peripheral function to which it is dedicated may be determined by other bits
such as those is the PADIR.
7.14.5 Port A Examples
The following paragraphs discuss various ways some of the port A pins can be configured.
Figure 7-97 and Figure 7-98 show block diagrams of the PA0 and PA1 pins.
PA0 can be configured as a general-purpose I/O pin, but not an open-drain pin. It may also
be the RXD1 pin for SCC1 in the NMSI mode. If PA0 is configured as a general-purpose I/
O pin, then the RXD1 input is internally grounded. If SCC1 is connected to a TDM or is not
used, then PA0 may be used as general-purpose I/O.
PA1 can be configured as a general-purpose I/O pin, either open-drain or not. It may also
be the TXD1 pin for SCC1 in the NMSI mode. If TXD1 is configured as an output on PA1
and the OD1 bit is set in PAODR, then TXD1 will be output from SCC1 as an open-drain
output. If PA1 is configured as a general-purpose I/O pin, then the TXD1 output is not con-
nected externally. If SCC1 is connected to a TDM or is not used, then PA1 may be used as
a general-purpose I/O.
Figure 7-97. Parallel Block Diagram for PA0
MUX
0
1
EN
0
1
RXD1/PA0
PIN
MUX
EN
1
0
RXD1
TO
SCC1
16 BITS
TO
PADAT
BIT 0
OUTPUT
LATCH
PADIR
16 BITS
PAPAR
EN
CPM
PRIORITY
RESOLVER
REQUEST
TO THE IMB AT
PROGRAMMABLE
LEVEL (1–7)
PORT C11–PORT C0
TIMER1
TIMER2
TIMER3
TIMER4
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
SPI
PIP
IDMA1
IDMA2
SDMA BUS ERROR
RISC TIMER TABLE
12
32-BIT
CPM
INTERRUPT
PENDING
REGISTER
(CPIR)
CPM
VECTOR
GENERATION
LOGIC
INTERRUPT
ARBITRATION
ID IS FIXED AT
LEVEL 8.
8-BIT INTERRUPT
VECTOR (LOWER
5 BITS FIXED,
UPPER 3 BITS
PROGRAMMABLE).
8
INTERMODULE BUS (IMB)
SOURCES
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Freescale Semiconductor, Inc.
For More Information On This Product,
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