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CPU32+
MC68360 USER’S MANUAL
5.7.2.2 CALCULATE EFFECTIVE ADDRESS. The calculate EA table indicates the num-
ber of clock periods needed for the processor to calculate a specified EA. The timing is
equivalent to fetch EA except there is no read cycle. The tail and cycle time are reduced by
the amount of time the read would occupy. The total number of clock cycles is outside the
parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle
number. All timing data assumes two-clock reads and writes.
Instruction
Head
Tail
Cycles
Notes
Dn
–
0(0/0/0)
–
An
–
0(0/0/0)
–
(An)
1
0
2(0/0/0)
–
(An)
+
1
0
2(0/0/0)
–
(An)
2
0
2(0/0/0)
–
(d16,An) or (d16,PC)
1
3(0/1/0)
1,3
(xxx).W
1
3(0/1/0)
1
(xxx).L
1
3
5(0/2/0)
1
(d8,An,Xn.Sz × Sc) or (d8,PC,Xn.Sz × Sc)
4
0
6(0/1/0)
2,3,4
(0) (All Suppressed)
2
0
4(0/1/0)
4
(d16)
1
5(0/2/0)
1,4
(d32)
1
3
7(0/3/0)
1,4
(An)
1
0
4(0/1/0)
4
(Xm.Sz
× Sc)
4
0
6(0/1/0)
2,4
(An,Xm.Sz
× Sc)
4
0
6(0/1/0)
2,4
(d16,An) or (d16,PC)
1
5(0/2/0)
1,3,4
(d32,An) or (d32,PC)
1
3
7(0/3/0)
1,3,4
(d16,An,Xm) or (d16,PC,Xm)
2
0
6(0/2/0)
3,4
(d32,An,Xm) or (d32,PC,Xm)
1
7(0/3/0)
1,3,4
(d16,An,Xm.Sz × Sc) or (d16,PC,Xm.Sz × Sc)
2
0
6(0/2/0)
2,3,4
(d32,An,Xm.Sz × Sc) or (d32,PC,Xm.Sz × Sc)
1
7(0/3/0)
1,2,3,4
NOTES:
1. Replacement fetches overlap the head of the operation by the amount specified in the tail.
2. Size and scale of the index register do not affect execution time.
3. The PC may be substituted for the base address register An.
4. When adjusting the prefetch time for slower buses, extra clocks may be subtracted from the head
until the head reaches zero, at which time additional clocks must be added to both the tail and cycle
counts.
5. Timing is calculated with the CPU32+ in 16-bit mode
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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