![](http://datasheet.mmic.net.cn/30000/MC68EN360FE33_datasheet_2368935/MC68EN360FE33_308.png)
System Integration Module (SIM60)
6-64
MC68360 USER’S MANUAL
6.13 PROGRAMMING MODEL
The user interfaces with the memory controller using eight identical sets of two registers, the
BR and OR. There are also two global registers in the memory controller: the GMR and the
MSTAT.
6.13.1 Global Memory Register (GMR)
The 32-bit read-write GMR contains selections that are common to the entire memory con-
troller: DRAM refresh properties, DRAM bank properties, SRAM bank properties, and some
global SRAM/DRAM properties. The reserved bits (4–0) should be written with zero.
SUPERVISOR SPACE ONLY
The following bits are used for DRAM refresh properties.
RCNT7–RCNT0—Refresh Counter Period
These bits determine the refresh period according to the following equation:
Example: For a 25-MHz system clock and a required refresh rate of 15.6
s per row, the
RFCNT value should be 24 (decimal). 24/(25 MHz/16) = 15.36
s, which is less than the
required refresh period of 15.6
s.
RFEN—Refresh Enable
0 = DRAM refresh is disabled.
1 = DRAM refresh is enabled.
RCYC1–RCYC0—Refresh Cycle Length
These bits determine the length of a refresh cycle.
00 = The refresh cycle is 4 clocks long, and RAS is negated for 3 phases prior to being
asserted.
01 = The refresh cycle is 6 clocks long, and RAS is negated for 5 phases prior to being
asserted.
10 = The refresh cycle is 7 clocks long, and RAS is negated for 5 phases prior to being
asserted.
11 = The refresh cycle is 8 clocks long, and RAS is negated for 5 phases prior to being
asserted.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RCNT7
RCNT6
RCNT5
RCNT4
RCNT3
RCNT2
RCNT1
RCNT0
RFEN
RCYC1
RCYC0
PGS2
PGS1
PGS0
DPS1
DPS0
0000000000000000
15
14
13
12
11
10
9876543210
WBT40
WBTQ
SYNC
EMWS
OPAR
PBEE
TSS40
NCS
DWQ
DW40
GAMX
—————
0001001000000000
Refresh period
=
RFCNT+1
System clk/16
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.