参数资料
型号: MCR705JP7CDWE
厂商: Freescale Semiconductor
文件页数: 116/164页
文件大小: 0K
描述: MCU 8BIT 224B RAM 28-SOIC
标准包装: 26
系列: HC05
核心处理器: HC05
芯体尺寸: 8-位
速度: 2.1MHz
连通性: SIO
外围设备: POR,温度传感器,WDT
输入/输出数: 22
程序存储器容量: 6KB(6K x 8)
程序存储器类型: OTP
RAM 容量: 224 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
数据转换器: A/D 4x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
包装: 管件
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
55
Chapter 7
Parallel Input/Output
7.1 Introduction
The MC68HC705JJ7 has 14 bidirectional input/output (I/O) pins which form two parallel I/O ports, A
and B. The MC68HC705JP7 has 22 bidirectional I/O pins which form three parallel I/O ports, A, B and C.
Each I/O pin is programmable as an input or an output. The contents of the data direction registers
determine the data direction of each of the I/O pins. All I/O pins have software programmable pulldown
devices which can be enabled or disabled globally by the SWPDI bit in the mask option register (MOR).
7.2 Port A
Port A is a 6-bit, general-purpose, bidirectional I/O port with these features:
Individual programmable pulldown devices
High current sinking capability on all port A pins, with a maximum total for port A
High current sourcing capability on all port A pins, with a maximum total for port A
External interrupt capability (pins PA3–PA0)
7.2.1 Port A Data Register
The port A data register (PORTA) contains a bit for each of the port A pins. When a port A pin is
programmed to be an output, the state of its data register bit determines the state of the output pin. When
a port A pin is programmed to be an input, reading the port A data register returns the logic state of the
pin. The upper two bits of the port A data register will always read as logic 0s.
PA5–PA0 — Port A Data Bits
These read/write bits are software programmable. Data direction of each bit is under the control of the
corresponding bit in the port A data direction register (DDRA). Reset has no effect on port A data.
Address:
$0000
Bit 7
654321
Bit 0
Read:
0
PA5
PA4
PA3
PA2
PA1
PA0
Write:
Reset:
Unaffected by reset
Alternate:
KYBD3
KYBD2
KYBD1
KYBD0
= Unimplemented
Figure 7-1. Port A Data Register (PORTA)
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