参数资料
型号: MCR705JP7CDWE
厂商: Freescale Semiconductor
文件页数: 130/164页
文件大小: 0K
描述: MCU 8BIT 224B RAM 28-SOIC
标准包装: 26
系列: HC05
核心处理器: HC05
芯体尺寸: 8-位
速度: 2.1MHz
连通性: SIO
外围设备: POR,温度传感器,WDT
输入/输出数: 22
程序存储器容量: 6KB(6K x 8)
程序存储器类型: OTP
RAM 容量: 224 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
数据转换器: A/D 4x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
包装: 管件
Parallel Input/Output
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
68
Freescale Semiconductor
7.4.3 Port C Pulldown Devices
All port C pins can have software programmable pulldown devices enabled or disabled globally by the
SWPDI bit in the MOR. These pulldown devices are individually controlled by the write-only pulldown
register A (PDRA) shown in Figure 7-3. PDICH controls the upper four pins (PC7–PC4) and PDICL
controls the lower four pins (PC3–PC0). Clearing the PDICH or PDICL bits in the PDRA turns on the
pulldown devices if the port C pin is an input. Reading the PDRA returns undefined results since it is a
write-only register. Reset clears the PDICH and PDICL bits, which turns on all the port C pulldown
devices.
7.4.4 Port C Logic
Figure 7-15 shows the I/O logic of port C.
When a port C pin is programmed as an output, reading the port bit actually reads the value of the data
latch and not the voltage on the pin itself. When a port C pin is programmed as an input, reading the port
bit reads the voltage level on the pin. The data latch can always be written, regardless of the state of its
DDR bit. Table 7-4 summarizes the operations of the port C pins.
Figure 7-15. Port C I/O Circuit
PCx
PORT C DATA
REGISTER
BIT PCx
READ $0006
WRITE $0002
READ $0002
WRITE $0010
PULLDOWN
DEVICE
RESET
INTERNAL
D
AT
A
B
U
S
WRITE $0006
DATA DIRECTION
REGISTER C
BIT DDRCx
PULLDOWN
REGISTER A
BIT PDICx
R
SWPDI
MASK OPTION REGISTER ($1FF1)
HIGH SINK/SOURCE
CURRENT CAPABILITY
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