参数资料
型号: MCR705JP7CDWE
厂商: Freescale Semiconductor
文件页数: 140/164页
文件大小: 0K
描述: MCU 8BIT 224B RAM 28-SOIC
标准包装: 26
系列: HC05
核心处理器: HC05
芯体尺寸: 8-位
速度: 2.1MHz
连通性: SIO
外围设备: POR,温度传感器,WDT
输入/输出数: 22
程序存储器容量: 6KB(6K x 8)
程序存储器类型: OTP
RAM 容量: 224 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
数据转换器: A/D 4x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
包装: 管件
Analog Control Register
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
77
CHG
The CHG enable bit allows direct control of the charge current source and the discharge device and
also reflects the state of the discharge device. This bit is cleared by a reset of the device.
1 = If the ISEN bit is also set, the charge current source is sourcing current out of the PB0/AN0 pin.
Writing a logic 1 enables the charging current out of the PB0/AN0 pin.
0 = The discharge device is sinking current into the PB0/AN0 pin. Writing a logic 0 disables the
charging current and enables the discharging current into the PB0/AN0 pin, if the ISEN bit is
also set.
ATD1–ATD2
The ATD1–ATD2 enable bits select one of the four operating modes used for making A/D conversions
via the single-slope method.These four modes are given in Table 8-3. These bits have no effect if the
ISEN enable bit is cleared. These bits are cleared by a reset of the device and thereby return the
analog subsystem to the manual A/D conversion method.
Address:
$001D
Bit 7
654321
Bit 0
Read:
CHG
ATD2
ATD1
ICEN
CPIE
CP2EN
CP1EN
ISEN
Write:
Reset:
00000000
Figure 8-5. Analog Control Register (ACR)
Table 8-3. A/D Conversion Options
A/D
Option
Mode
Charge
Control
A/D Options
Current Flow
to/from PB0/AN0
ISEN
ATD2
ATD1
CHG
Disabled
Current
source and
discharge
disabled
0
XXX
Current control disabled,
no source or sink current
100
1
Begin sourcing current
when the CHG bit is set
and continue to source
current until the CHG bit is
cleared.
110
1
The CHG bit remains set
until the next time ICF
occurs.
3
Automatic
charge and
discharge
(OCF–ICF)
synchronized
to timer
111
0
The CHG bit remains
cleared until the next time
OCF occurs.
111
1
The CHG bit remains set
until the next time ICF
occurs.
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