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参数资料
型号： MCR705JP7CDWE
厂商： Freescale Semiconductor
文件页数： 164/164页
文件大小： 0K
描述： MCU 8BIT 224B RAM 28-SOIC
标准包装： 26
系列： HC05
核心处理器： HC05
芯体尺寸： 8-位
速度： 2.1MHz
连通性： SIO
外围设备： POR，温度传感器，WDT
输入/输出数： 22
程序存储器容量： 6KB（6K x 8）
程序存储器类型： OTP
RAM 容量： 224 x 8
电压 - 电源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
数据转换器： A/D 4x12b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 28-SOIC（0.295"，7.50mm 宽）
包装： 管件
SIOP Registers
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
99
9.3.2 SIOP Status Register
The SIOP status register (SSR) is located at address $000B and contains two read-only bits. Figure 9-5
shows the position of each bit in the register and indicates the value of each bit after reset.
SPIF — Serial Port Interrupt Flag
The SPIF is a read-only status bit that is set on the last rising edge of SCK and indicates that a data
transfer has been completed. It has no effect on any future data transfers and can be ignored. The
SPIF bit can be cleared by reading the SSR followed by a read or write of the SDR or by writing a logic
1 to the SPIR bit in the SCR. If the SPIF is cleared before the last rising edge of SCK it will be set again
on the last rising edge of SCK. Reset clears the SPIF bit.
1 = Serial transfer complete, serial interrupt if the SPIE bit in SCR is set
0 = Serial transfer in progress or serial interface idle
DCOL — Data Collision Bit
The DCOL is a read-only status bit which indicates that an illegal access of the SDR has occurred. The
DCOL bit will be set when reading or writing the SDR after the first falling edge of SCK and before SPIF
is set. Reading or writing the SDR during this time will result in invalid data being transmitted or
received. The DCOL bit is cleared by reading the SSR (when the SPIF bit is set) followed by a read or
write of the SDR. If the last part of the clearing sequence is
done after another transfer has started, the DCOL bit will be set again. Reset clears the DCOL bit.
1 = Illegal access of the SDR occurred
0 = No illegal access of the SDR detected
Table 9-1. SIOP Clock Rate Selection
SPR1
SPR0
SIOP Clock Rate
Oscillator Frequency
Divided by:
00
64
01
32
10
16
11
8
Address:
$000B
Bit 7
654321
Bit 0
Read:
SPIF
DCOL
000000
Write:
Reset:
00000000
= Unimplemented
Figure 9-5. SIOP Status Register (SSR)
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