参数资料
型号: MT45W2MV16BAFB-706LIT
元件分类: SRAM
英文描述: 2M X 16 PSEUDO STATIC RAM, 70 ns, PBGA54
封装: FBGA-54
文件页数: 11/55页
文件大小: 816K
代理商: MT45W2MV16BAFB-706LIT
2 MEG x 16
ASYNC/PAGE/BURST CellularRAM MEMORY
ADVANCE
09005aef80ec6f63
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Burst CellularRAM_32.fm - Rev. A 2/18/04 EN
19
2004 Micron Technology, Inc. All Rights Reserved.
WAIT Configuration (BCR[8])
Default = WAIT Transitions One Clock
Before Data Valid/Invalid
The WAIT configuration bit is used to determine
when WAIT transitions between the asserted and the
de-asserted state with respect to valid data presented on
the data bus. The memory controller will use the WAIT
signal to coordinate data transfer during synchronous
READ and WRITE operations. When BCR[8] = 0, data
will be valid or invalid on the clock edge immediately
after WAIT transitions to the de-asserted or asserted
state, respectively (Figures 16 and 18). When A8 = 1, the
WAIT signal transitions one clock period prior to the
data bus going valid or invalid (Figures 17 and 16).
WAIT Polarity (BCR[10])
Default = WAIT Active HIGH
The WAIT polarity bit indicates whether an asserted
WAIT output should be HIGH or LOW. This bit will
determine whether the WAIT signal requires a pull-up
or pull-down resistor to maintain the de-asserted
state.
Figure 16: WAIT Configuration (BCR[8] = 0)
NOTE:
1. Note: Data valid/invalid immediately after WAIT
transitions (BCR[8] = 0). See Figure 18.
Figure 17: WAIT Configuration (BCR[8] = 1)
NOTE:
1. Note: Valid/invalid data delayed for one clock after
WAIT transitions (BCR[8] = 1). See Figure 18.
Figure 18: WAIT Configuration During Burst Operation1
NOTE:
1. Non-default BCR setting: WAIT active LOW.
WAIT
DQ[15:0]
CLK
Data[0]
Data[1]
Data immediately valid (or invalid)
High-Z
WAIT
D[15:0]
CLK
Data[0]
Data valid (or invalid) after one clock delay
High-Z
WAIT
DQ[15:0]
CLK
D[0]
D[1]
BCR[8] = 0
DATA VALID IN CURRENT CYCLE
BCR[8] = 1
DATA VALID IN NEXT CYCLE
DON’T CARE
D[2]
D[3]
D[4]
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