参数资料
型号: MT45W2MV16BAFB-706LIT
元件分类: SRAM
英文描述: 2M X 16 PSEUDO STATIC RAM, 70 ns, PBGA54
封装: FBGA-54
文件页数: 45/55页
文件大小: 816K
代理商: MT45W2MV16BAFB-706LIT
2 MEG x 16
ASYNC/PAGE/BURST CellularRAM MEMORY
ADVANCE
09005aef80ec6f63
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Burst CellularRAM_32.fm - Rev. A 2/18/04 EN
5
2004 Micron Technology, Inc. All Rights Reserved.
General Description
Micron CellularRAM products are high-speed,
CMOS dynamic random access memories developed
for
low-power,
portable
applications.
The
MT45W2MW16BA is a 32Mb device organized as 2
Meg x 16 bits. These devices include an industry-
standard burst mode Flash interface that dramatically
increases read/write bandwidth compared with other
low-power SRAM or Pseudo SRAM offerings.
To operate seamlessly on a burst Flash bus, Cellular-
RAM products incorporate a transparent self-refresh
mechanism. The hidden refresh requires no additional
support from the system memory controller and has
no significant impact on device read/write perfor-
mance.
Two user-accessible control registers define device
operation. The bus configuration register (BCR)
defines how the CellularRAM device interacts with the
system memory bus and is nearly identical to its coun-
terpart on burst mode Flash devices. The refresh con-
figuration register (RCR) is used to control how refresh
is performed on the DRAM array. These registers are
automatically loaded with default settings during
power-up and can be updated anytime during normal
operation.
Special attention has been focused on standby cur-
rent consumption during self refresh. CellularRAM
products include three system-accessible mechanisms
to minimize standby current. Partial array refresh
(PAR) limits refresh to only that part of the DRAM array
that contains essential data. Temperature compen-
sated refresh (TCR) uses an on-chip sensor to adjust
the refresh rate to match the device temperature. The
refresh rate decreases at lower temperatures to mini-
mize current consumption during standby. TCR can
also be set by the system for maximum device temper-
atures of +85°C, +45°C, and +15°C. Deep power-down
(DPD) halts the refresh operation altogether and is
used when no vital information is stored in the device.
These three refresh mechanisms are accessed through
the RCR.
Figure 2: Functional Block Diagram—2 Meg x 16
NOTE:
Functional block diagrams illustrate simplified device operation. See truth table, ball descriptions, and timing
diagrams for detailed information.
A[20:0]
Input/
Output
MUX
and
Buffers
Control
Logic
2,048K x 16
DRAM
MEMORY
ARRAY
CE#
WE#
OE#
CLK
ADV#
CRE
WAIT
LB#
UB#
DQ[7:0]
DQ[15:8]
Address Decode
Logic
Refresh Configuration
Register (RCR)
Bus Configuration
Register (BCR)
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