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参数资料
| 型号： | MT45W2MV16BAFB-706LIT |
| 元件分类： | SRAM |
| 英文描述： | 2M X 16 PSEUDO STATIC RAM, 70 ns, PBGA54 |
| 封装： | FBGA-54 |
| 文件页数： | 53/55页 |
| 文件大小： | 816K |
| 代理商： | MT45W2MV16BAFB-706LIT |
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2 MEG x 16
ASYNC/PAGE/BURST CellularRAM MEMORY
ADVANCE
09005aef80ec6f63
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Burst CellularRAM_32.fm - Rev. A 2/18/04 EN
7
2004 Micron Technology, Inc. All Rights Reserved.
NOTE:
1. CLK may be HIGH or LOW, but must be static during async read, async write, burst suspend, and DPD modes; and to
achieve standby power during standby and active modes.
2. The WAIT polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are
affected. When only UB# is in the select mode, DQ[15:8] are affected.
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any
external influence.
6. VIN = VCCQ or 0V; all device balls must be static (unswitched) in order to achieve standby current.
7. DPD is maintained until RCR is reconfigured.
8. Burst mode operation is initialized through the bus configuration register (BCR[15]).
Table 2:
Bus Operations—Asynchronous Mode
MODE
POWER
CLK1
ADV#
CE#
OE#
WE#
CRE
LB#/
UB#
WAIT2
DQ[15:0]3
NOTES
Read
Active
X
L
H
L
Low-Z
Data-Out
4
Write
Active
X
L
X
L
Low-Z
Data-In
4
Standby
X
H
X
L
X
High-Z
5, 6
No Operation
Idle
X
L
X
L
X
Low-Z
X
4, 6
Configuration
Register
Active
X
L
LHLH
X
Low-Z
High-Z
DPD
Deep
Power-Down
X
H
X
High-Z
7
Table 3:
Bus Operations—Burst Mode
MODE
POWER
CLK1
ADV#
CE#
OE#
WE#
CRE
LB#/
UB#
WAIT2
DQ[15:0]3
NOTES
Async Read
Active
X
L
H
L
Low-Z
Data-Out
4
Async Write
Active
X
L
X
L
Low-Z
Data-In
4
Standby
X
H
X
L
X
High-Z
5, 6
No Operation
Idle
X
L
X
L
X
Low-Z
X
4, 6
Initial Burst
Read
Active
L
X
H
L
Low-Z
Data-Out
4, 8
Initial Burst
Write
Active
L
H
L
X
Low-Z
Data-In
4, 8
Burst
Continue
Active
H
L
X
L
X
Low-Z
Data-In or
Data-Out
4, 8
Burst Suspend
Active
X
L
H
X
L
X
Low-Z
High-Z
4, 8
Configuration
Register
Active
L
H
L
H
X
Low-Z
High-Z
8
DPD
Deep
Power-Down
XX
H
XXXX
High-Z
7
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