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参数资料
| 型号： | MT45W2MV16BAFB-706LIT |
| 元件分类： | SRAM |
| 英文描述： | 2M X 16 PSEUDO STATIC RAM, 70 ns, PBGA54 |
| 封装： | FBGA-54 |
| 文件页数： | 8/55页 |
| 文件大小： | 816K |
| 代理商： | MT45W2MV16BAFB-706LIT |
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2 MEG x 16
ASYNC/PAGE/BURST CellularRAM MEMORY
ADVANCE
09005aef80ec6f63
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Burst CellularRAM_32.fm - Rev. A 2/18/04 EN
16
2004 Micron Technology, Inc. All Rights Reserved.
Software Access
Software access of the configuration registers uses a
sequence of asynchronous READ and asynchronous
WRITE operations. The contents of the configuration
registers can be read or modified using the software
sequence.
The configuration registers are loaded using a four-
step sequence consisting of two asynchronous READ
operations followed by two asynchronous WRITE
operations (see Figure 14). The read sequence is virtu-
ally identical except that an asynchronous READ is
performed during the fourth operation (see Figure 15).
The address used during all READ and WRITE opera-
tions is the highest address of the CellularRAM device
being accessed (1FFFFFh for 32Mb); the contents of
this address are not changed by using this sequence.
The data value presented during the third operation
(WRITE) in the sequence defines whether the BCR or
the RCR is to be accessed. If the data is 0000h, the
sequence will access the RCR; if the data is 0001h, the
sequence will access the BCR. During the fourth oper-
ation, the data bus is used to transfer data in to or out
of the configuration registers.
The use of the software sequence does not affect the
ability to perform the standard (CRE-controlled)
method of loading the configuration registers. How-
ever, the software nature of this access mechanism
eliminates the need for the control register enable
(CRE) pin. If the software mechanism is used, the CRE
pin can simply be tied to VSS. The port line often used
for CRE control purposes is no longer required.
Software access of the RCR should not be used to
enter or exit DPD.
Figure 14: Load Configuration Register
Figure 15: Read Configuration Register
NOTE:
CE# must be HIGH for 150ns before performing the
cycle that reads a configuration register.
ADDRESS
(MAX)
ADDRESS
(MAX)
ADDRESS
(MAX)
ADDRESS
(MAX)
XXXXh
RCR: 0000h
BCR: 0001h
CR VALUE
IN
ADDRESS
CE#
OE#
WE#
LB#/UB#
DATA
DON'T CARE
READ
WRITE
ADDRESS
(MAX)
ADDRESS
(MAX)
ADDRESS
(MAX)
ADDRESS
(MAX)
XXXXh
CR VALUE
OUT
ADDRESS
CE#
OE#
WE#
LB#/UB#
DATA
DON'T CARE
READ
WRITE
READ
RCR: 0000h
BCR: 0001h
NOTE
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT45W2MV16PFA-70 WT | 制造商:Micron Technology Inc 功能描述:2MX16 PSRAM PLASTIC WIRELESS TEMP FBGA 1.8V ASYNCH PSEUDO ST - Trays |
| MT45W2MW16BABB-706 L WT | 功能描述:IC PSRAM 32MBIT 70NS 54VFBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:378 系列:- 格式 - 存储器:闪存 存储器类型:FLASH 存储容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-CBGA 供应商设备封装:48-CBGA（7x7） 包装:托盘 |
| MT45W2MW16BABB-706 L WT TR | 制造商:Micron Technology Inc 功能描述:PSRAM ASYNC 1 32MBIT 2MX16 70NS 54VFBGA - Tape and Reel |
| MT45W2MW16BABB-706 WT | 制造商:Micron Technology Inc 功能描述:PSRAM Async 1 32M-Bit 2M x 16 70ns 54-Pin VFBGA Tray 制造商:Micron Technology Inc 功能描述:PSRAM ASYNC 1 32MBIT 2MX16 70NS 54VFBGA - Trays 制造商:Micron Technology Inc 功能描述:IC PSRAM 32MBIT 70NS 54VFBGA |
| MT45W2MW16BABB-706 WT TR | 功能描述:IC PSRAM 32MBIT 70NS 54VFBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:96 系列:- 格式 - 存储器:闪存 存储器类型:FLASH 存储容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并联 电源电压:2.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 |
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