参数资料
型号: MT45W2MV16BAFB-706LIT
元件分类: SRAM
英文描述: 2M X 16 PSEUDO STATIC RAM, 70 ns, PBGA54
封装: FBGA-54
文件页数: 55/55页
文件大小: 816K
代理商: MT45W2MV16BAFB-706LIT
2 MEG x 16
ASYNC/PAGE/BURST CellularRAM MEMORY
ADVANCE
09005aef80ec6f63
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Burst CellularRAM_32.fm - Rev. A 2/18/04 EN
9
2004 Micron Technology, Inc. All Rights Reserved.
Functional Description
In general, the MT45W2MW16BA device is a high-
density alternative to SRAM and Pseudo SRAM prod-
ucts, popular in low-power, portable applications.
The MT45W2MW16BA contains 33,554,432 bits
organized as 2,097,152 addresses by 16 bits. The device
implements the same high-speed bus interface found
on burst mode Flash products.
The CellularRAM bus interface supports both asyn-
chronous and burst mode transfers. Page mode
accesses are also included as a bandwidth-enhancing
extension to the asynchronous read protocol.
Power-Up Initialization
CellularRAM products include an on-chip voltage
sensor used to launch the power-up initialization pro-
cess. Initialization will configure the BCR and the RCR
with their default settings (see Table 5 on page 17 and
Table 8 on page 21). VCC and VCCQ must be applied
simultaneously. When they reach a stable level at or
above 1.70V, the device will require 150s to complete
its self-initialization process. During the initialization
period, CE# should remain HIGH. When initialization
is complete, the device is ready for normal operation.
Figure 3: Power-Up Initialization
Timing
Bus Operating Modes
The MT45W2MW16BA CellularRAM product incor-
porates a burst mode interface found on Flash prod-
ucts targeting low-power, wireless applications. This
bus interface supports asynchronous, page mode, and
burst mode read and write transfers. The specific inter-
face supported is defined by the value loaded into the
bus configuration register. Page mode is controlled by
the refresh configuration register (RCR[7]).
Asynchronous Mode
CellularRAM products power up in the asynchro-
nous operating mode. This mode uses the industry-
standard SRAM control bus (CE#, OE#, WE#, LB#/
UB#). READ operations (Figure 4) are initiated by
bringing CE#, OE#, and LB#/UB# LOW while keeping
WE# HIGH. Valid data will be driven out of the I/Os
after the specified access time has elapsed. WRITE
operations (Figure 5) occur when CE#, WE#, and LB#/
UB# are driven LOW. During asynchronous WRITE
operations, the OE# level is a “Don't Care,” and WE#
will override OE#. The data to be written is latched on
the rising edge of CE#, WE#, or LB#/UB# (whichever
occurs first). Asynchronous operations (page mode
disabled) can either use the ADV input to latch the
address, or ADV can be driven LOW during the entire
READ/WRITE operation.
During asynchronous operation, the CLK input must
be static (HIGH or LOW—no transition). WAIT will be
driven while the device is enabled and its state should
be ignored.
Figure 4: READ Operation (ADV = LOW)
NOTE:
ADV must remain LOW for page mode operation.
Figure 5: WRITE Operation (ADV = LOW)
Vcc
VccQ
Device Initialization
Vcc = 1.70V
Device ready for
normal operation
tPU > 150s
ADDRESS VALID
DATA
CE#
DON’T CARE
DATA VALID
OE#
WE#
LB#/UB#
tRC = READ Cycle Time
ADDRESS
ADDRESS VALID
DATA
CE#
DON’T CARE
DATA VALID
OE#
WE#
LB#/UB#
tWC = WRITE Cycle Time
ADDRESS
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