参数资料
型号: MT45W2MV16BAFB-706LIT
元件分类: SRAM
英文描述: 2M X 16 PSEUDO STATIC RAM, 70 ns, PBGA54
封装: FBGA-54
文件页数: 21/55页
文件大小: 816K
代理商: MT45W2MV16BAFB-706LIT
2 MEG x 16
ASYNC/PAGE/BURST CellularRAM MEMORY
ADVANCE
09005aef80ec6f63
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Burst CellularRAM_32.fm - Rev. A 2/18/04 EN
28
2004 Micron Technology, Inc. All Rights Reserved.
NOTE:
1. See the Appendix at the end of this data sheet.
2. Low-Z to High-Z timings are tested with the circuit shown in Figure 21 on page 25. The High-Z timings measure a
100mV transition from either VOH or VOL toward VCCQ/2.
3. High-Z to Low-Z timings are tested with the circuit shown in Figure 21 on page 25. The Low-Z timings measure a
100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.
Table 18:
Asynchronous WRITE Cycle Timing Requirements
PARAMETER
SYMBOL
-701, -706
-856
UNITS
NOTES
MIN
MAX
MIN
MAX
Address and ADV# LOW Setup Time
tAS
00
ns
Address Hold from ADV# Going HIGH
tAVH
55
ns
Address Setup to ADV# Going HIGH
tAVS
10
ns
Address Valid to End of Write
tAW
70
85
ns
LB#/UB# Select to End of Write
tBW
70
85
ns
Maximum CE# Pulse Width
tCEM
10
s
1
CE# LOW to WAIT Valid
tCEW
1
7.5
1
7.5
ns
Async Address-to-Burst Transition Time
tCKA
70
85
ns
CE# Low to ADV# HIGH
tCVS
10
ns
Chip Enable to End of Write
tCW
70
85
ns
Data Hold from Write Time
tDH
00
ns
Data WRITE Setup Time
tDW
23
ns
1
Chip Disable to WAIT High-Z Output
tHZ
88
ns
Chip Enable to Low-Z Output
tLZ
10
ns
3
End WRITE to Low-Z Output
tOW
55
ns
3
ADV# Pulse Width
tVP
10
ns
ADV# Pulse Width HIGH
tVPH
10
ns
ADV# Setup to End of WRITE
tVS
70
85
ns
WRITE Cycle Time
tWC
70
85
ns
WRITE to DQ High-Z Output
tWHZ
88
ns
2
WRITE Pulse Width
tWP
46
55
ns
1
WRITE Pulse Width HIGH
tWPH
10
ns
WRITE Recovery Time
tWR
00
ns
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