参数资料
型号: MT45W2MV16BAFB-706LIT
元件分类: SRAM
英文描述: 2M X 16 PSEUDO STATIC RAM, 70 ns, PBGA54
封装: FBGA-54
文件页数: 15/55页
文件大小: 816K
代理商: MT45W2MV16BAFB-706LIT
2 MEG x 16
ASYNC/PAGE/BURST CellularRAM MEMORY
ADVANCE
09005aef80ec6f63
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Burst CellularRAM_32.fm - Rev. A 2/18/04 EN
22
2004 Micron Technology, Inc. All Rights Reserved.
Deep Power-Down (RCR[4])
Default = DPD Disabled
The deep power-down bit enables and disables all
refresh-related activity. This mode is used if the system
does not require the storage provided by the Cellular-
RAM device. Any stored data will become corrupted
when DPD is enabled. When refresh activity has been
re-enabled, the CellularRAM device will require 150s
to perform an initialization procedure before normal
operations can resume.
Deep power-down is enabled when RCR[4] = 0, and
remains enabled until RCR[4] is set to “1.” DPD should
not be enabled or disabled with the software access
sequence; instead, use CRE to access the RCR.
Temperature Compensated Refresh (RCR[6:5])
Default = On-Chip Temperature Sensor
This CellularRAM device includes an on-chip tem-
perature sensor that automatically adjusts the refresh
rate according to the operating temperature. The on-
chip TCR is enabled by clearing both of the TCR bits in
the refresh configuration register (RCR[6:5] = 00b). Any
other TCR setting enables a fixed refresh rate. When
the on-chip temperature sensor is enabled, the device
continually adjusts the refresh rate according to the
operating temperature.
The TCR bits also allow for adequate fixed-rate
refresh at three different temperature thresholds
(+15°C, +45°C, and +85°C). The setting selected must
be for a temperature higher than the case tempera-
ture of the CellularRAM device. If the case tempera-
ture is +35°C, the system can minimize self refresh
current consumption by selecting the +45°C setting.
The +15°C setting would result in inadequate
refreshing and cause data corruption.
Page Mode Operation (RCR[7])
Default = Disabled
The page mode operation bit determines whether
page mode is enabled for asynchronous READ opera-
tions. In the power-up default state, page mode is dis-
abled.
Table 9:
32Mb Address Patterns for PAR (RCR[4] = 1)
RCR[2]
RCR[1]
RCR[0]
ACTIVE SECTION
ADDRESS SPACE
SIZE
DENSITY
0
Full die
000000h–1FFFFFh
2 Meg x 16
32Mb
0
1
Three-quarters of die
000000h–17FFFFh
1.5 Meg x 16
24Mb
0
1
0
One-half of die
000000h–0FFFFFh
1 Meg x 16
16Mb
0
1
One-quarter of die
000000h–07FFFFh
512K x 16
8Mb
1
0
None of die
0
0 Meg x 16
0Mb
1
0
1
Three-quarters of die
080000h–1FFFFFh
1.5 Meg x 16
24Mb
1
0
One-half of die
100000h–1FFFFFh
1 Meg x 16
16Mb
1
One-quarter of die
180000h–1FFFFFh
512K x 16
8Mb
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