参数资料
型号: MT45W2MV16BAFB-706LIT
元件分类: SRAM
英文描述: 2M X 16 PSEUDO STATIC RAM, 70 ns, PBGA54
封装: FBGA-54
文件页数: 49/55页
文件大小: 816K
代理商: MT45W2MV16BAFB-706LIT
2 MEG x 16
ASYNC/PAGE/BURST CellularRAM MEMORY
ADVANCE
09005aef80ec6f63
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Burst CellularRAM_32.fm - Rev. A 2/18/04 EN
53
2004 Micron Technology, Inc. All Rights Reserved.
APPENDIX A
How Extended Timings Impact
CellularRAMTM Operation
Introduction
This note describes CellularRAM timing require-
ments in systems that perform extended operations.
CellularRAM products use a DRAM technology that
periodically requires refresh to ensure against data cor-
ruption. CellularRAM devices include on-chip circuitry
that performs the required refresh in a manner that is
completely transparent in systems with normal bus
timings. The refresh circuitry imposes constraints on
timings in systems that take longer than 10s to com-
plete an operation. WRITE operations are affected if
the device is configured for asynchronous operation.
Both READ and WRITE operations are affected if the
device is configured for page or burst-mode operation.
Asynchronous WRITE Operation
The timing parameters provided in Table 18 on
page 28 require that all WRITE operations must be
completed within 10s. After completing a WRITE
operation, the device must either enter standby (by
transitioning CE# HIGH), or else perform a second
operation (READ or WRITE) using a new address. Fig-
ures 45 and 46 demonstrate these constraints as they
apply during an asynchronous (page-mode-disabled)
operation. Either the CE# active period (tCEM in
Figure 45) or the address valid period (tTM in
Figure 46) must be less than 10s during any WRITE
operation, otherwise, the extended WRITE timings
must be used.
Figure 45: Extended Timing for tCEM
Figure 46: Extended Timing for tTM
CE#
ADDRESS
tCEM 10s
<
CE#
ADDRESS
<
tTM
10s
Table 49:
Extended Cycle Impact on READ and WRITE Cycles
PAGE MODE
TIMING CONSTRAINT
READ CYCLE
WRITE CYCLE
Asynchronous
Page Mode Disabled
tCEM and tTM > 10s
(See Figures 45 and 46 above.)
No impact.
Must use extended WRITE timing.
Asynchronous
Page Mode Enabled
tCEM > 10s
(See Figure 45 above.)
Not allowed.
Burst
tCEM > 10s
(See Figure 45 above.)
Burst must cross a row boundary within 10s.
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