- 您现在的位置：买卖IC网 > PDF目录224506 > MT47H128M8HQ-187ELAT:E 128M X 8 DDR DRAM, 0.35 ns, PBGA60 PDF资料下载
参数资料
| 型号： | MT47H128M8HQ-187ELAT:E |
| 元件分类： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| 封装： | 8 X 11.50 MM, ROHS COMPLIANT, FBGA-60 |
| 文件页数： | 69/133页 |
| 文件大小： | 9170K |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页当前第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页
18. The inputs to the DRAM must be aligned to the associated clock, that is, the actual clock
that latches it in. However, the input timing (in ns) references to the tCK (AVG) when
determining the required number of clocks. The following input parameters are deter-
mined by taking the specified percentage times the tCK (AVG) rather than tCK: tIPW,
tDIPW, tDQSS, tDQSH, tDQSL, tDSS, tDSH, tWPST, and tWPRE.
19. The DRAM output timing is aligned to the nominal or average clock. Most output param-
eters must be derated by the actual jitter error when input clock jitter is present; this
will result in each parameter becoming larger. The following parameters are required to
be derated by subtracting tERR5per (MAX): tAC (MIN), tDQSCK (MIN), tLZDQS (MIN), tLZDQ
(MIN), tAON (MIN); while the following parameters are required to be derated by sub-
tracting tERR5per (MIN): tAC (MAX), tDQSCK (MAX), tHZ (MAX), tLZDQS (MAX), tLZDQ
(MAX), tAON (MAX). The parameter tRPRE (MIN) is derated by subtracting tJITper (MAX),
while tRPRE (MAX), is derated by subtracting tJITper (MIN). The parameter tRPST (MIN) is
derated by subtracting tJITdty (MAX), while tRPST (MAX), is derated by subtracting tJITd-
ty (MIN). Output timings that require tERR5per derating can be observed to have offsets
relative to the clock; however, the total window will not degrade.
20. When DQS is used single-ended, the minimum limit is reduced by 100ps.
21. tHZ and tLZ transitions occur in the same access time windows as valid data transitions.
These parameters are not referenced to a specific voltage level, but specify when the
device output is no longer driving (tHZ) or begins driving (tLZ).
22. tLZ (MIN) will prevail over a tDQSCK (MIN) + tRPRE (MAX) condition.
23. This is not a device limit. The device will operate with a negative value, but system per-
formance could be degraded due to bus turnaround.
24. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command.
The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were
previously in progress on the bus. If a previous WRITE was in progress, DQS could be
HIGH during this time, depending on tDQSS.
25. The intent of the “Don’t Care” state after completion of the postamble is that the DQS-
driven signal should either be HIGH, LOW, or High-Z, and that any signal transition
within the input switching region must follow valid input requirements. That is, if DQS
transitions HIGH (above VIH[DC]min), then it must not transition LOW (below VIH[DC]) prior
to tDQSH (MIN).
26. Referenced to each output group: x4 = DQS with DQ0–DQ3; x8 = DQS with DQ0–DQ7;
x16 = LDQS with DQ0–DQ7; and UDQS with DQ8–DQ15.
27. The data valid window is derived by achieving other specifications: tHP (tCK/2), tDQSQ,
and tQH (tQH = tHP - tQHS). The data valid window derates in direct proportion to the
clock duty cycle and a practical data valid window can be derived.
28. tQH = tHP - tQHS; the worst case tQH would be the lesser of tCL (ABS) MAX or
tCH (ABS) MAX times tCK (ABS) MIN - tQHS. Minimizing the amount of tCH (AVG) offset
and value of tJITdty will provide a larger tQH, which in turn will provide a larger valid
data out window.
29. This maximum value is derived from the referenced test load. tHZ (MAX) will prevail
over tDQSCK (MAX) + tRPST (MAX) condition.
30. The values listed are for the differential DQS strobe (DQS and DQS#) with a differential
slew rate of 2 V/ns (1 V/ns for each signal). There are two sets of values listed: tDSa, tDHa
and tDSb, tDHb. The tDSa, tDHa values (for reference only) are equivalent to the baseline
values of tDSb, tDHb at VREF when the slew rate is 2 V/ns, differentially. The baseline val-
ues, tDSb, tDHb, are the JEDEC-defined values, referenced from the logic trip points. tDSb
is referenced from VIH(AC) for a rising signal and VIL(AC) for a falling signal, while tDHb is
referenced from VIL(DC) for a rising signal and VIH(DC) for a falling signal. If the differen-
tial DQS slew rate is not equal to 2 V/ns, then the baseline values must be derated by
adding the values from Table 30 (page 61) and Table 31 (page 62). If the DQS differ-
ential strobe feature is not enabled, then the DQS strobe is single-ended and the
baseline values must be derated using Table 32 (page 63). Single-ended DQS data tim-
ing is referenced at DQS crossing VREF. The correct timing values for a single-ended DQS
1Gb: x4, x8, x16 DDR2 SDRAM
AC Timing Operating Specifications
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. S 10/09 EN
40
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
相关PDF资料 |
PDF描述 |
|---|---|
| MT48LC2M32B1TG-7 | 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86 |
| MT48LC32M4A2P-7ELIT:G | 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| MT55L256L18FT-12TR | 256K X 18 ZBT SRAM, 9 ns, PQFP100 |
| MT55L256L32FT-12 | 256K X 32 ZBT SRAM, 9 ns, PQFP100 |
| MT55L512V18PF-6 | 512K X 18 ZBT SRAM, 3.5 ns, PBGA165 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT47H128M8HQ-25AT | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HQ-25EAT | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DDR2 SDRAM |
发布紧急采购，3分钟左右您将得到回复。