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| 型号： | ORT82G5-2BM680 |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| 封装： | PLASTIC, BGA-680 |
| 文件页数： | 17/110页 |
| 文件大小： | 1459K |
| 代理商： | ORT82G5-2BM680 |
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14
Lattice Semiconductor
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
ORT82G5 Overview (continued)
The ORT82G5 FPSC combines 8 channels of high-
speed full duplex serial links (up to 3.5 Gbits/s) with
400k usable gate FPGA. The major functional blocks in
the ASB core are two quad-channel serializer-deserial-
izers (SERDES) including 8b/10b encoder/decoder
and dedicated PLLs, XAUI or bre-channel link-state-
machine, 4-to-1 or 1-to-4 MUX/deMUX, multichannel
alignment FIFO, microprocessor interface, and 4k x 36
RAM blocks.
Serializer and Deserializer (SERDES)
The SERDES block is a quad transceiver for serial data
transmission, with a selectable data rate of 1.0—
1.25 Gbits/s, 2.0—2.5 Gbits/s, or 3.125—3.5 Gbits/s. It
is designed to operate in Ethernet, bre channel, XAUI,
InniBand, or backplane applications. It features high-
speed 8b/10b parallel I/O interfaces, and high-speed
CML interfaces.
The quad transceiver is controlled and congured with
an 8-bit microprocessor interface through the FPGA.
Each channel has dedicated registers that are read-
able and writable. The quad device also contains glo-
bal registers for control of common circuitry and
functions.
8b/10b Encoding/Decoding
The ORT82G5 facilitates high-speed serial transfer of
data in a variety of applications including Gbit Ethernet,
bre channel, serial backplanes, and proprietary links.
The SERDES provides 8b/10b coding/decoding for
each channel. The 8b/10b transmission code includes
serial encoding/decoding rules, special characters, and
error detection.
In the receive direction, the user can disable the
8b/10b decoder to receive raw 10 bit words which will
be rate reduced by the SERDES. If this mode is cho-
sen, the user must bypass the multichannel alignment
FIFOs. In the transmit direction, the 8b/10b encoder
must always be enabled.
Clocks
The SERDES block contains its own dedicated PLLs
for transmit and receive clock generation. The user
provides a reference clock of the appropriate fre-
quency. The receiver PLLs extract the clock from the
serial input data and retime the data with the recovered
clock.
MUX/DeMUX Block
The purpose of the MUX/deMUX block is to provide a
wide, low-speed interface at the FPGA portion of the
ORT82G5 for each channel or data lane.
The interface to the SERDES macro runs at 1/10th the
bit rate of the data lane. The MUX/deMUX converts the
data rate and bit-width so the FPGA core can run at
1/4th this frequency. This implies a range of 25—78
MHz for the data in and out of the FPGA.
The MUX/deMUX block in the ORT82G5 is a 4-channel
block. It provides an interface between each quad
channel SERDES and the FPGA logic.
Multichannel Alignment FIFOs
The ORT82G5 has a total of 8 channels (4 per SER-
DES). The incoming data of these channels can be
synchronized in several ways, or they can be indepen-
dent of one other. For example, all four channels in a
SERDES can be aligned together to form a communi-
cation channel with a bandwidth of 10 Gbits/s. Alterna-
tively, two channels within a SERDES can be aligned
together; channel A and B and/or channel C and D.
Optionally, the alignment can be extended across SER-
DES to align all 8 channels. Individual channels within
an alignment group can be disabled (i.e., power down)
without disrupting other channels.
XAUI or Fibre-Channel Link State Machine
Two separate link state machines are included in the
ORT82G5. A XAUI compliant link state machine is
included in the embedded core to implement the IEEE
802.3ae v2.1 standard. A separate state machine for
bre-channel is also provided.
Dual Port RAMs
There are two independent memory blocks in the ASB.
Each memory block has a capacity of 4k word by
36 bits. It has one read port, one write port, and four
byte-write-enable (active-low) signals. The read data
from the memory block is registered so that it works as
a pipelined synchronous memory block.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ORT82G5-2BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2F680C | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2F680I | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2FN680C | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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