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| 型号： | ORT82G5-2BM680 |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| 封装： | PLASTIC, BGA-680 |
| 文件页数： | 27/110页 |
| 文件大小： | 1459K |
| 代理商： | ORT82G5-2BM680 |
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Lattice Semiconductor
23
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Backplane Transceiver Core Detailed
Description (continued)
Byte Alignment
When ENBYSYNC = 1, the ORT82G5 recognizes the
comma sequence and aligns the 10-bit comma contain-
ing character to the word boundary. BYTSYNC = 1
when the parallel output word contains a byte-aligned
comma containing character. The BYTSYNC ag will
continue to pulse a logic 1 whenever a byte aligned
comma containing character is at the parallel output
port.
Link State Machines
Two link state machines are included in the ORT82G5,
one for XAUI applications and a second for bre-chan-
nel applications.
The bre-channel link state machine is responsible for
establishing a valid link between the transmitter and the
receiver and for maintaining link synchronization. The
machine wakes up in the loss of synchronization state
upon powerup reset. This is indicated by WDSYNC = 0.
While in this state, the machine looks for a particular
number of consecutive idle ordered sets without any
invalid data transmission in between before declaring
synchronization achieved. Synchronization achieved is
indicated by asserting WDSYNC = 1. Specically, the
machine looks for three continuous idle ordered sets
without any misaligned comma character or any run-
ning disparity based code violation in between. In the
event of any such code violation, the machine would
reset itself to the ground state and start its search for
the idle ordered sets again. An example of a valid
sequence for achieving link synchronization would be
K28.5 D21.4 D21.5 D21.5 repeated 3 times.
In the synchronization achieved state, the machine
constantly monitors the received data and looks for any
kind of code violation that might result due to running
disparity errors. If it were to receive four such consecu-
tive invalid words, the link machine loses its synchroni-
zation and once again enters the loss of
synchronization state (LOS). A pair of valid words
received by the machine overcomes the effect of a pre-
viously encountered code violation. LOS is indicated
by the status of WDSYNC output which now transitions
from 1 to 0. At this point the machine attempts to
establish the link yet again. Figure 6 shows the state
diagram for the bre-channel link state machine.
In the ORT82G5 LOS is indicated by
DEMUXWAS_[AA, AB,... BD] register bit. This bit is 0
during LOS.
2266(F)
Figure 6. Fibre-Channel Link State Machine State Diagram
LOS = 1
OS: IDLE ORDERED SET (A 4 CHARACTER BASED WORD HAVING COMMA AS THE 1ST CHARACTER)
VW
RST
LINK SYNCHRONIZATION ACHIEVED (WDSYNC = 1)
OS
CV
OS
CV
VW
2 VW
a
b
c
d
e
h
g
f
LOSS OF SYNCHRONIZATION (WDSYNC = 0)
LSM_ENABLE
+
POWERUP RESET
VW: VALID WORD (A 4 CHARACTER BASED WORD HAVING NO CODE VIOLATION)
CV: CODE VIOLATION (RUNNING DISPARITY BASED ON ILLEGAL COMMA POSITION)
相关PDF资料 |
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| OS10040280G-012 | FIBER OPTIC RECEIVER, 1290-1600nm, PANEL MOUNT, FC/APC CONNECTOR |
| OT-WBSC-Y-A-10-X-9-M-3-05-FA | FIBER OPTIC SPLITTER/COUPLER, 1X2PORT, 10.0, PANEL MOUNT, FC/APC CONNECTOR |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ORT82G5-2BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2F680C | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2F680I | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2FN680C | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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