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参数资料
型号： ORT82G5-2BM680
厂商： LATTICE SEMICONDUCTOR CORP
元件分类： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封装： PLASTIC, BGA-680
文件页数： 30/110页
文件大小： 1459K
代理商： ORT82G5-2BM680
26
Lattice Semiconductor
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Backplane Transceiver Core Detailed
Description (continued)
MUX/DeMUX Block
Transmit Path (FPGA → Backplane)
The MUX is responsible for taking 36 bits of data/con-
trol at the low-speed transmit interface and up-convert-
ing it to 9 bits of data/control at the SERDES transmit
interface.
The MUX has 2 clock domains: one based on a clock
received from the SERDES; the other that comes from
the FPGA at 1/4 the frequency of the SERDES clock.
The time sequence of interleaving data/control values
is shown in Figure 8 below.
The low-speed transmit interface consists of a clock,
4 data byte values and a control bit for each of the byte
values. The data bytes are conveyed to the MUX via
the TWDx[31:0] ports. The control bits are TCOM-
MAx[3:0]. The clock is TSYS_CLK_[AA, AB, AC.... BD]
or TSYS_CLK_x for the sake of brevity.
Both the data and control are strobed into the MUX at
this interface on the rising edge of TSYS_CLK_x.
Besides taking in a clock for capture, the interface
sends back a clock of the same frequency, but arbitrary
phase. This clock, TCK78(A,B), is derived from one of
the 4 channels of MUX. Within each MUX is a divide-
by-4 of the SERDES STBC311x clock used in synchro-
nizing the transmit data words to the STBC311x clock
domain. TCKSEL bits select the source channel of
TCK78. The selection of clock source for TCK78(A,B) is
shown in Table 8.
Table 8. TCK78 selection
TCKSEL0
TCKSEL1
Clock Source
00
Channel A
10
Channel B
01
Channel C
11
Channel D
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