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参数资料
型号： ORT82G5-2BM680
厂商： LATTICE SEMICONDUCTOR CORP
元件分类： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封装： PLASTIC, BGA-680
文件页数： 85/110页
文件大小： 1459K
代理商： ORT82G5-2BM680
76
Lattice Semiconductor
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Pin Information (continued)
This section describes device I/O signals to/from the embedded core excluding the signals at the CIC boundary.
Table 30. FPSC Function Pin Description
Symbol
I/O
Description
Common Signals for Both SERDES A and B
PASB_RESETN
I
Active low reset for the embedded core. All non-SERDES specific registers
(addresses 308***, 309***, 30A***) in the embedded core are not reset.
PASB_TRISTN
I
Active low 3-state for embedded core output buffers.
PASB_PDN
I
Active low power down of all SERDES blocks and associated I/Os.
PASB_TESTCLK
I
Clock input for BIST and loopback test.
PBIST_TEST_ENN
I
Selection of PASB_TESTCLK input for BIST test.
PLOOP_TEST_ENN
I
Selection of PASB_TESTCLK input for loopback test.
PMP_TESTCLK
I
Clock input for microprocessor in test mode.
PMP_TESTCLK_ENN
I
Selection of PMP_TESTCLK in test mode.
PSYS_DOBISTN
I
Input to start BIST test.
PSYS_RSSIG_ALL
O
Output result of BIST test.
SERDES A and B Pins
REFCLKN_A
I
CML reference clock input—SERDES A.
REFCLKP_A
I
CML reference clock input—SERDES A.
REFCLKN_B
I
CML reference clock input—SERDES B.
REFCLKP_B
I
CML reference clock input—SERDES B.
REXT_A
I
Reference resistor—SERDES A.
REXT_B
I
Reference resistor—SERDES B.
REXTN_A
I
Reference resistor—SERDES A. A 3.32 K ± 1% resistor must be con-
nected across REXT_A and REXTN_A.
REXTN_B
I
Reference resistor—SERDES B. A 3.32 K ± 1% resistor must be con-
nected across REXT_B and REXTN_B.
HDINN_AA
I
High-speed CML receive data input—SERDES A, channel A.
HDINP_AA
I
High-speed CML receive data input—SERDES A, channel A.
HDINN_AB
I
High-speed CML receive data input—SERDES A, channel B.
HDINP_AB
I
High-speed CML receive data input—SERDES A, channel B.
HDINN_AC
I
High-speed CML receive data input—SERDES A, channel C.
HDINP_AC
I
High-speed CML receive data input—SERDES A, channel C.
HDINN_AD
I
High-speed CML receive data input—SERDES A, channel D.
HDINP_AD
I
High-speed CML receive data input—SERDES A, channel D.
HDINN_BA
I
High-speed CML receive data input—SERDES B, channel A.
HDINP_BA
I
High-speed CML receive data input—SERDES B, channel A.
HDINN_BB
I
High-speed CML receive data input—SERDES B, channel B.
HDINP_BB
I
High-speed CML receive data input—SERDES B, channel B.
HDINN_BC
I
High-speed CML receive data input—SERDES B, channel C.
HDINP_BC
I
High-speed CML receive data input—SERDES B, channel C.
HDINN_BD
I
High-speed CML receive data input—SERDES B, channel D.
HDINP_BD
I
High-speed CML receive data input—SERDES B, channel D.
相关PDF资料
PDF描述
ORT82G5-3BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
OS10040280G-012 FIBER OPTIC RECEIVER, 1290-1600nm, PANEL MOUNT, FC/APC CONNECTOR
OT-WBSC-Y-A-10-X-9-M-3-05-FA FIBER OPTIC SPLITTER/COUPLER, 1X2PORT, 10.0, PANEL MOUNT, FC/APC CONNECTOR
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