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参数资料
型号： ORT82G5-2BM680
厂商： LATTICE SEMICONDUCTOR CORP
元件分类： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封装： PLASTIC, BGA-680
文件页数： 62/110页
文件大小： 1459K
代理商： ORT82G5-2BM680
Lattice Semiconductor
55
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Memory Map (continued)
Table 18. Memory Map (continued)
Addr
(Hex)
Reg
#
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Default
Value
SERDES B Global Control Register (Acts on Channels A, B, C, and D)
30105
—
GPRBS_B
Global
Enable. The
GPRBS bit
globally
enables the
PRBS gener-
ators and
checkers all
four channels
of SERDES B
when GPRBS
= 1. GPRBS =
0 on device
reset.
GMASK_B
Global Mask.
The GMASK
globally
masks all the
channel
alarms of
SERDES B
when GMASK
= 1. This pre-
vents all the
transmit and
receive
alarms from
generating an
interrupt.
GMASK = 1
on device
reset.
GSWRST_B
RESET Function.
The GSWRST bit
provides the same
function as the
hardware reset for
the transmit and
receive sections of
all four channels of
ASERDES B,
except that the
device congura-
tion settings are
not affected when
GSWRST is
asserted.
GSWRST = 0 on
device reset. This
is not a self-clear-
ing bit. Once set, it
must be cleared by
writing a 0 to it.
GPWRDNT_B
Powerdown
Transmit
Function.
When
GPWRDNT =
1, sections of
the transmit
hardware for
all four chan-
nels of SER-
DES B are
powered down
to conserve
power.
GPWRDNT =
0 on device
reset.
GPWRDNR_B
Powerdown
Receive Func-
tion. When
GPWRDNR =
1, sections of
the receive
hardware for
all four chan-
nels of SER-
DES B are
powered down
to conserve
power.
GPWRDNR =
0 on device
reset.
GTRISTN_B
Active-Low
TRISTN Func-
tion. When
GTRISTN = 0,
the CMOS out-
put buffers for
SERDES B
are 3-stated.
GTRISTN = 1
on device
reset.
—
GTESTEN_B
Test Enable
Control. When
GTESTEN = 1,
the transmit and
receive sections
of all four chan-
nels of SER-
DES B are
placed in test
mode. GTES-
TEN = 0 on
device reset.
44
30106
—
TestMode
—
RSVD
00
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ORT82G5-2F680I 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORT82G5-2FN680C 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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