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参数资料
| 型号： | ORT82G5-2BM680 |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| 封装： | PLASTIC, BGA-680 |
| 文件页数： | 96/110页 |
| 文件大小： | 1459K |
| 代理商： | ORT82G5-2BM680 |
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86
Lattice Semiconductor
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Pin Information (continued)
Package Pinouts
Table 33 provides the package pin and pin function for the ORT82G5 FPSC and packages. The bond pad name is
identied in the PIO nomenclature used in the ORCA Foundry design editor. The Bank column provides information
as to which output voltage level bank the given pin is in. The Group column provides information as to the group of
pins the given pin is in. This is used to show which VREF pin is used to provide the reference voltage for single-
ended limited-swing I/Os. If none of these buffer types (such as SSTL, GTL, HSTL) are used in a given group, then
the VREF pin is available as an I/O pin.
When the number of FPGA bond pads exceeds the number of package pins, bond pads are unused. When the
number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects).
When a package pin is to be left as a no connect for a specic die, it is indicated as a note in the device column for
the FPGA. The tables provide no information on unused pads.
As shown in the pair columns in Table 33, differential pairs and physical locations are numbered within each bank
(e.g., L19C-A0 is the nineteenth pair in an associated bank). A C indicates complementary differential, whereas a T
indicates true differential. An _A0 indicates the physical location of adjacent balls in either the horizontal or vertical
direction. Other physical indicators are as follows:
■
_A1 indicates one ball between pairs.
■
_A2 indicates two balls between pairs.
■
_D0 indicates balls are diagonally adjacent.
■
_D1 indicates balls are diagonally adjacent, separated by one physical ball.
VREF pins, shown in the Pin Description column in Table 33, are associated to the bank and group (e.g.,
VREF_TL_01 is the VREF for group one of the top left (TL) bank.
相关PDF资料 |
PDF描述 |
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| ORT82G5-3BM680 | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| OS10040280G-012 | FIBER OPTIC RECEIVER, 1290-1600nm, PANEL MOUNT, FC/APC CONNECTOR |
| OT-WBSC-Y-A-10-X-9-M-3-05-FA | FIBER OPTIC SPLITTER/COUPLER, 1X2PORT, 10.0, PANEL MOUNT, FC/APC CONNECTOR |
| OT-WBSC-Y-A-50-13-9-F-1-05-FA | FIBER OPTIC SPLITTER/COUPLER, 1X2PORT, 50.0, PANEL MOUNT, FC/APC CONNECTOR |
| OT-WBSC-Y-A-50-X-9-O-1-99-SA | FIBER OPTIC SPLITTER/COUPLER, 1X2PORT, 50.0, PANEL MOUNT, SC/APC CONNECTOR |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ORT82G5-2BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2F680C | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2F680I | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2FN680C | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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