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参数资料
| 型号： | ORT82G5-2BM680 |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| 封装： | PLASTIC, BGA-680 |
| 文件页数： | 43/110页 |
| 文件大小： | 1459K |
| 代理商： | ORT82G5-2BM680 |
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38
Lattice Semiconductor
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Backplane Transceiver Core Detailed Description (continued)
Parallel Loopback at the SERDES Boundary
The parallel loopback involves the parallel buses LDIN[9:0] and LDOUT[9:0]. The loopback connection is made
such that LDIN[9:0] is logically equivalent to LDOUT[9:0]. In the parallel loopback mode, the LDOUT[9:0] pins
remain active. The receive data are sourced at the HDINP, HDINN pins and detected at the HDOUTP, HDOUTN
pins. The device is otherwise in its normal mode of operation. The data rate selection bits TXHR and RXHR in the
channel conguration registers must be congured to carry the same value and the PRBS generator and checker
are excluded by setting the PRBS conguration bit to 0. Also, the 8b/10b encoder and decoder are excluded from
the loopback path by setting the 8b10bT and 8b10bR conguration bits to 0. Table 16 illustrates the control inter-
face register conguration for the parallel loopback.
Table 16. Parallel Loopback Conguration
Parallel Loopback at MUX/DeMUX Boundary Excluding SERDES
This is a low-frequency testmode. This parallel loopback involves the parallel buses SRBDx[9:0] and STBDx[9:0].
The loopback connection is made such that SRBDx[9:0] is logically equivalent to STBDx[9:0] and STBDx[9:0]
remains active, thus bypassing the SERDES. Data can be sent from the FPGA through TWDxx signals and moni-
tored on MRWDxx signals. This test is enabled by setting the pin PLOOP_TEST_ENN to 1. PASB_TESTCLK must
be running in this mode at 4x frequency of RSYS_CLK[A1,A2,B1,B2] or TSYS_CLK_[AA, AB . . . BD].
Register
Address
Bit Value
Bit Name
Comments
30002, 30012, 30022, 30032,
30102, 30112, 30122, 30132
Bit 0 = 0 or 1
TXHR
Set to 0 or 1. TXHR and RXHR bits must be set to
the same value.
30002, 30012, 30022, 30032,
30102, 30112, 30122, 30132
Bit 7 = 0
8B10BT
Set to 0. The 8b/10b encoder is excluded from
the loopback path. The 8b/10b encoder and
decoder selection control bits must both be set to
0.
30003, 30013, 30023, 30033,
30103, 30113, 30123, 30133
Bit 0 = 0 or 1
RXHR
Set to 0 or 1. TXHR and RXHR bits must be set to
the same value.
30003, 30013, 30023, 30033,
30103, 30113, 30123, 30133
Bit 3 = 0
8B10BR
Set to 0. The 8b/10b decoder is excluded from
the loopback path. The 8b/10b encoder and
decoder selection control bits must both be set to
0.
30004, 30014, 30024, 30034,
30104, 30114, 30124, 30134
Bit 0 = 0
PRBS
Set to 0.
30004, 30014, 30024, 30034,
30104, 30114, 30124, 30134
Bit 7 = 1
—
Set to 1 if the loopback is done on a per-channel
basis. However, if the loopback is done on all the
four channels in a quad macro, this bit can be set
to 0 but bit 7 of register 5 must be set to 1.
30005, 30105
Bit 7 = 1
—
Set to 1 if the loopback is done globally on all four
channels in a quad macro.
30006, 30106
Bits[4:0] =00001
—
Set to 00001.
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| ORT82G5-2BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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| ORT82G5-2FN680C | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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