参数资料
型号: ORT82G5-2BM680
厂商: LATTICE SEMICONDUCTOR CORP
元件分类: FPGA
英文描述: FPGA, 1296 CLBS, 380000 GATES, PBGA680
封装: PLASTIC, BGA-680
文件页数: 79/110页
文件大小: 1459K
代理商: ORT82G5-2BM680
70
Lattice Semiconductor
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
HSI Electrical and Timing Characteristics (continued)
Table 24. Reference Clock Specications (REFINP and REFINN)
Note: Additional (<10 MHz) REFCLK jitter will increase the total transmit output jitter.
Table 25. Channel Output Jitter (1.25 Gbits/s)
Table 26. Channel Output Jitter (2.5 Gbits/s)
Table 27. Serial Output Timing and Levels (CML I/O)
Note: Differential swings are based on direct CML to CML connections.
Parameter
Min
Typ
Max
Unit
Frequency Range
100
175
MHz
Frequency Tolerance
– 100
100
ppm
Duty Cycle (Measured at 50% Amplitude Point)
40
50
60
%
Rise Time
500
1000
ps
Fall Time
500
1000
ps
P–N Input Skew
75
ps
Differential Amplitude
500
800
2 x VDD
mVp-p
Common Mode Level
Vsingle-ended/2
0.75
VDD15 – (Vsingle-ended/2)V
Single-Ended Amplitude
250
400
VDD15
mVp-p
Input Capacitance (at REFINP)
5
pF
Input Capacitance (at REFINPIT)
3
pF
Inband (< 10 MHz) Jitter (2.5 Gbits/s)
30
psp-p
Inband (< 10 MHz) Jitter (1.25 Gbits/s)
60
psp-p
Parameter
Min
Typ
Max
Unit
Deterministic
0.08
UIp-p
Random
0.12
UIp-p
Total
0.20
UIp-p
Parameter
Min
Typ
Max
Unit
Deterministic
0.10
UIp-p
Random
0.14
UIp-p
Total
0.24
UIp-p
Parameter
Min
Typ
Max
Unit
Rise Time (20%—80%)
50
80
110
ps
Fall Time (80%—20%)
50
80
110
ps
Common Mode
VDDOB –0.30
VDDOB –0.25
VDDOB –0.15
V
Differential Swing (Full Amplitude)
800
900
1100
mVp-p
Differential Swing (Half Amplitude)
400
500
600
mVp-p
Output Load
50
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