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| 型号： | ORT82G5-2BM680 |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| 封装： | PLASTIC, BGA-680 |
| 文件页数： | 18/110页 |
| 文件大小： | 1459K |
| 代理商： | ORT82G5-2BM680 |
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Lattice Semiconductor
15
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
ORT82G5 Overview (continued)
FPGA Interface
The FPGA logic will receive/transmit 32-bits of data (up
to 78 MHz) and 4-bits of k-ctrl characters (in 8b/10b
mode) from/to the embedded core. There are a maxi-
mum of 8 such streams in each direction. Data sent to
the FPGA can be aligned using comma (/K/) characters
or /A/ character (as specied in IEEE 802.3ae for XAUI
based interfaces). The alignment character is made
available to the FPGA along with the data. A comma
character is a special character that contains a unique
pattern (0011111 or its complement 1100000) in the
10-bit space that makes it useful for delimiting word
boundaries. The special characters K28.1, K28.5 and
K28.7 contain this comma sequence and are treated as
valid comma characters by the SERDES.
If the receive channel alignment FIFOs are bypassed,
then each channel will provide its own receive clock in
addition to data and k-character detect signals. If the
8b/10b decoders are bypassed, then 40-bit data
streams are passed to the FPGA logic. No channel
alignment can be done in 8b-/10b-bypass mode. For
transmit direction (FPGA to core), data and k-ctrl char-
acters will be sent from FPGA to core for each channel.
FPSC Conguration
Conguration of the ORT82G5 occurs in two stages:
FPGA bitstream conguration and embedded core
setup.
FPGA Conguration
Prior to becoming operational, the FPGA goes through
a sequence of states, including powerup, initialization,
conguration, start-up, and operation. The FPGA logic
is congured by standard FPGA bit stream congura-
tion means as discussed in the Series 4 FPGA data
sheet. The options for the embedded core are set via
registers that are accessed through the FPGA system
bus. The system bus can be driven by an external Pow-
erPC compliant microprocessor via the MPI block or via
a user master interface in FPGA logic. A simple IP
block, that drives the system by using the user register
interface and very little FPGA logic, is available in the
MPI/System Bus Application Note. This IP block sets
up the embedded core via a state machine and allows
the ORT82G5 to work in an independent system with-
out an external microprocessor interface.
Backplane Transceiver Core Detailed
Description
SERDES
A detailed block diagram of the receive and transmit
data paths for a single channel of the SERDES is
shown in Figure 3.
The transmitter section accepts either 8-bit unencoded
data or 10-bit encoded data at the parallel input port. It
also accepts the low-speed reference clock at the REF-
CLK input and uses this clock to synthesize the internal
high-speed serial bit clock. The serialized data are
available at the differential CML output terminated in
50 or 75 to drive either an optical transmitter or
coaxial media or circuit board/backplane.
The receiver section receives high-speed serial data at
its differential CML input port. These data are fed to the
clock recovery section which generates a recovered
clock and retimes the data. This means that the receive
clocks are asynchronous between channels. The
retimed data are deserialized and presented as a 10-bit
encoded or a 8-bit unencoded parallel data on the out-
put port. Two-phase receive byte clocks are available
synchronous with the parallel words. The receiver also
optionally recognizes the comma characters or code
violations and aligns the bit stream to the proper word
boundary.
Bias Section
A fractional band-gap voltage generator is included on
the design. An external resistor (3.32 k ± 1%), con-
nected between the pins REXT and VSSREXT gener-
ates the bias currents within the chip. This resistor
should be able to handle at least 300 mA.
相关PDF资料 |
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| OS10040280G-012 | FIBER OPTIC RECEIVER, 1290-1600nm, PANEL MOUNT, FC/APC CONNECTOR |
| OT-WBSC-Y-A-10-X-9-M-3-05-FA | FIBER OPTIC SPLITTER/COUPLER, 1X2PORT, 10.0, PANEL MOUNT, FC/APC CONNECTOR |
| OT-WBSC-Y-A-50-13-9-F-1-05-FA | FIBER OPTIC SPLITTER/COUPLER, 1X2PORT, 50.0, PANEL MOUNT, FC/APC CONNECTOR |
| OT-WBSC-Y-A-50-X-9-O-1-99-SA | FIBER OPTIC SPLITTER/COUPLER, 1X2PORT, 50.0, PANEL MOUNT, SC/APC CONNECTOR |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ORT82G5-2BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2F680C | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2F680I | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2FN680C | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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