- 您现在的位置：买卖IC网 > PDF目录299581 > ORT82G5-2BM680 (LATTICE SEMICONDUCTOR CORP) FPGA, 1296 CLBS, 380000 GATES, PBGA680 PDF资料下载
参数资料
| 型号： | ORT82G5-2BM680 |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| 封装： | PLASTIC, BGA-680 |
| 文件页数： | 40/110页 |
| 文件大小： | 1459K |
| 代理商： | ORT82G5-2BM680 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页当前第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页
Lattice Semiconductor
35
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Backplane Transceiver Core Detailed Description (continued)
Note that any channel within an alignment group can be removed from that alignment group by setting
FMPU_STR_EN_XX to 0. The disabling of any channel(s) within an alignment group will not affect the operation of
the remaining active channels. If the active channels are synchronized, that synchronization will be maintained and
no data loss will occur.
Alignment can also be done between the receive channels on two ORT82G5 devices. Each of the two devices
needs to provide its aligned K_CTRL or other alignment character to the other device, which will delay reading from
a second alignment FIFO until all channels requesting alignment on the current device AND all channels request-
ing alignment on the other device are aligned (as indicated on the K_CTRL character). This second alignment
FIFO will be implemented in FPGA logic on the ORT82G5. This scheme also requires that the reference clock for
both devices be driven by the same signal.
XAUI Lane Alignment Function (Lane Deskew)
In XAUI mode, the receive section in each lane uses the /A/ code group to compensate for lane-to-lane skew. The
mechanism restores the timing relationship between the 4 lanes by lining up the /A/ characters into a column. Fig-
ure 2 shows the alignment of four lanes based on /A/ character. A minimum spacing of 16 code-groups implies that
at least ± 80 bits of skew compensation capability should be provided, which the ORT82G5 signicantly exceeds.
2392(F)
Figure 15. Deskew Lanes by Aligning /A/ Columns
Mixing Half-rate, Full-rate Modes
When channel alignment is enabled, all receive channels within an alignment group should be congured at the
same rate. For example, channels AA, AB, can be congured for twin alignment and full-rate mode, while channels
AC, AD that form an alignment group can be congured for half-rate mode. In quad alignment mode, each receive
quad can be congured in either half or full-rate mode.
When channel alignment is disabled (this control bit NOCHALGNX is available per quad) within a quad, any
receive channel within the quad can be used in half-rate or full-rate mode. The clocking strategy for half-rate mode
in both scenarios- (channel alignment enabled and disabled) is described in section Clocking Recommendations of
ORT82G5.
LANE 0
K
RR
K
R
K
R
K
R
K
RR
K
A
LANE 1
K
RR
K
R
K
R
K
R
K
RR
K
A
LANE 2
K
RR
K
R
K
R
K
R
K
RR
K
A
LANE 3
K
RR
K
R
K
R
K
R
K
RR
K
A
LANE 0
K
RR
K
R
K
R
K
R
K
RR
K
A
LANE 1
K
RR
K
R
K
R
K
R
K
RR
K
A
LANE 2
K
RR
K
R
K
R
K
R
K
RR
K
A
LANE 3
K
RR
K
R
K
R
K
R
K
RR
K
A
相关PDF资料 |
PDF描述 |
|---|---|
| ORT82G5-3BM680 | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| OS10040280G-012 | FIBER OPTIC RECEIVER, 1290-1600nm, PANEL MOUNT, FC/APC CONNECTOR |
| OT-WBSC-Y-A-10-X-9-M-3-05-FA | FIBER OPTIC SPLITTER/COUPLER, 1X2PORT, 10.0, PANEL MOUNT, FC/APC CONNECTOR |
| OT-WBSC-Y-A-50-13-9-F-1-05-FA | FIBER OPTIC SPLITTER/COUPLER, 1X2PORT, 50.0, PANEL MOUNT, FC/APC CONNECTOR |
| OT-WBSC-Y-A-50-X-9-O-1-99-SA | FIBER OPTIC SPLITTER/COUPLER, 1X2PORT, 50.0, PANEL MOUNT, SC/APC CONNECTOR |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ORT82G5-2BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2F680C | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2F680I | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2FN680C | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
发布紧急采购，3分钟左右您将得到回复。