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参数资料
型号： ORT82G5-2BM680
厂商： LATTICE SEMICONDUCTOR CORP
元件分类： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封装： PLASTIC, BGA-680
文件页数： 38/110页
文件大小： 1459K
代理商： ORT82G5-2BM680
Lattice Semiconductor
33
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Backplane Transceiver Core Detailed
Description (continued)
Table 10.
Definition of Bits of MRWDxy[39:0]
The use of the FIFO is controlled by conguration bits,
and the raw demultiplexed data can also be sent to the
FPGA directly, by passing the alignment FIFO. The
control register bits for alignment FIFO in ORT82G5
are described below.
Table 11. Multichannel Alignment Modes
Note: Where xx is one of A[A:D] and B[A:D].
To align all eight channels:
■
FMPU_SYNMODE_A[A:D] = 11
■
FMPU_SYNMODE_B[A:D] = 11
To align all four channels in SERDES A:
■
FMPU_SYNMODE_A[A:D] = 01
To align two channels in SERDES A:
■
FMPU_SYNMODE_A[A:B] = 10 for channel AA and
AB
■
FMPU_SYNMODE_A[C:D] = 10 for channel AC and
AD
Similar alignment can be dened for SERDES B.
To enable/disable synchronization signal of individual
channel within a multi-channel alignment group:
■
FMPU_STR_EN_xx = 1 enabled
■
FMPU_STR_EN_xx = 0 disabled
where xx is one of A[A:D] and B[A:D].
Bit Index
NOCHALGNx = 1
NOCHALGNx = 0
39
b9 of char 1
CH248_SYNCx
38
b8 of char 1
K_CTRL for char 1
37
b7 of char 1
36
b6 of char 1
35
b5 of char 1
34
b4 of char 1
33
b3 of char 1
32
b2 of char 1
31
b1 of char 1
30
b0 of char 1
29
b9 of char 2
n/c
28
b8 of char 2
K_CTRL for char 2
27
b7 of char 2
26
b6 of char 2
25
b5 of char 2
24
b4 of char 2
23
b3 of char 2
22
b2 of char 2
21
b1 of char 2
20
b0 of char 2
19
b9 of char 3
n/c
18
b8 of char 3
K_CTRL for char 3
17
b7 of char 3
16
b6 of char 3
15
b5 of char 3
14
b4 of char 3
13
b3 of char 3
12
b2 of char 3
11
b1 of char 3
10
b0 of char 3
09
b9 of char 4
n/c
08
b8 of char 4
K_CTRL for char 4
07
b7 of char 4
06
b6 of char 4
05
b5 of char 4
04
b4 of char 4
03
b3 of char 4
02
b2 of char 4
01
b1 of char 4
00
b0 of char 4
Register Bits
FMPU_SYNMODE_xx
[0:1]
Mode
00
No multichannel alignment.
10
Twin channel alignment.
01
Quad channel alignment.
11
Eight channel alignment.
相关PDF资料
PDF描述
ORT82G5-3BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
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