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参数资料
型号： ORT82G5-2BM680
厂商： LATTICE SEMICONDUCTOR CORP
元件分类： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封装： PLASTIC, BGA-680
文件页数： 51/110页
文件大小： 1459K
代理商： ORT82G5-2BM680
Lattice Semiconductor
45
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Memory Map (continued)
Table 18. Memory Map (continued)
Addr
(Hex)
Reg
#
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Default
Value
SERDES A Transmit Channel Conguration Registers (continued)
30032
—
TXHR_AD
Transmit Half
Rate Selec-
tion Bit, Bank
A, Channel
D. When
TXHR = 1,
the transmit-
ter samples
data on the
falling edge
of the TBC
clock. When
TXHR = 0,
the transmit-
ter samples
data on the
falling edge
of the double
rate clock
(derived from
TBC). TXHR
= 0 on device
reset.
PWRDNT_A
D
Transmit
Powerdown
Control Bit,
Bank A,
Channel D.
When
PWRDNT =
1, sections of
the transmit
hardware are
powered
down to con-
serve power.
PWRDNT = 0
on device
reset.
PE0_AD
Transmit Pre-
emphasis
Selection Bit
0, Bank A,
Channel D.
PE0,
together with
PE1, selects
one of three
preemphasis
settings for
the transmit
section. PE0
= 0 on device
reset.
PE1_AD
Transmit Pre-
emphasis
Selection Bit
1, Bank A,
Channel D.
PE1,
together with
PE0, selects
one of three
preemphasis
settings for
the transmit
section. PE1
= 0 on device
reset.
HAMP_AD
Transmit Half
Amplitude
Selection Bit,
Bank A,
Channel D.
When HAMP
= 1, the
transmit out-
put buffer
voltage swing
is limited to
half its ampli-
tude. Other-
wise, the
transmit out-
put buffer
maintains its
full voltage
swing. HAMP
= 0 on device
reset.
TBCKSEL_A
D
Transmit
Byte Clock
Selection Bit,
Bank A,
Channel D.
When TBCK-
SEL = 0, the
internal XCK
is selected.
Otherwise,
the TBC
clock is
selected.
TBCKSEL =
0 on device
reset.
RSVD
8B10BT_AD
Transmit 8B/
10B Encoder
Enable Bit,
Bank A,
Channel D.
When
8B10BT = 1,
the 8B/10B
encoder on
the transmit
path is
enabled. Oth-
erwise, it is
bypassed.
8B10BT = 0
on device
reset.
00
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ORT82G5-2FN680C 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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