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| 型号： | ORT82G5-2BM680 |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| 封装： | PLASTIC, BGA-680 |
| 文件页数： | 42/110页 |
| 文件大小： | 1459K |
| 代理商： | ORT82G5-2BM680 |
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Lattice Semiconductor
37
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Backplane Transceiver Core Detailed Description (continued)
Loopback Modes
The device can be exercised in four possible loopback modes. These loopback modes are identied as:
■
High-speed serial loopback
■
Parallel loopback at the SERDES boundary
■
Parallel loopback at MUX/deMUX boundary excluding SERDES
■
Operational mode full loopback using the PRBS generator/checker
These four loopback modes are described next.
High-Speed Serial Loopback
The high-speed serial loopback involves the transmit signal at the serial interface being looped back internally to
the receive circuitry. The serial loopback path does not include the high-speed input and output buffers. The
HDOUTP, HDOUTN outputs are active in this loopback mode, but the CML input buffers are powered down. The
data are sourced at the LDIN[9:0] pins and detected at the LDOUT[9:0] pins. The device is otherwise in its normal
mode of operation. The data rate selection bits, TXHR and RXHR, in the channel conguration registers must be
congured to carry the same value and the PRBS Generator and Checker are excluded by setting the PRBS con-
guration bit to 0. The 8b/10b encoder/decoder can optionally be congured into or out of the loopback path. The
following Table 15 illustrates the control interface register conguration for the high-speed serial loopback.
Table 15. High-Speed Serial Loopback Conguration
Register
Address
Bit Value
Bit Name
Comments
30002, 30012, 30022,
30032, 30102, 30112,
30122, 30132
Bit 0 = 0 or 1
TXHR
Set to 0 or 1. TXHR and RXHR bits must be set to the
same value.
30002, 30012, 30022,
30032, 30102, 30112,
30122, 30132
Bit 7 = 0 or 1
8B10BT
Set to 0 or 1. If set to 0, the 8b/10b encoder is excluded
from the loopback path. The 8b/10b encoder and decoder
selection control bits must both be set to the same value.
30003, 30013, 30023,
30033, 30103, 30113,
30123, 30133
Bit 0 = 0 or 1
RXHR
Set to 0 or 1. TXHR and RXHR bits must be set to the
same value.
30003, 30013, 30023,
30033, 30103, 30113,
30123, 30133
Bit 3 = 0 or 1
8B10BR
Set to 0 or 1. If set to 0, the 8b/10b decoder is excluded
from the loopback path. The 8b/10b encoder and decoder
selection control bits must both be set to the same value.
30004, 30014, 30024,
30034, 30104, 30114,
30124, 30134
Bit 0 = 0
PRBS
Set to 0.
30801, 30901
Bit 0 =1
(Channel A)
Bit 1 = 1
(Channel B)
Bit 2 = 1
(Channel C)
Bit 3 = 1
(Channel D)
LOOPENB_x Set any of the bits 0-3 to 1 to do serial loopback on the cor-
responding channel.
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