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| 型号： | ORT82G5-2BM680 |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| 封装： | PLASTIC, BGA-680 |
| 文件页数： | 2/110页 |
| 文件大小： | 1459K |
| 代理商： | ORT82G5-2BM680 |
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10
Lattice Semiconductor
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
System-Level Features
The Series 4 also provides system-level functionality by
means of its microprocessor interface, embedded sys-
tem bus, quad-port embedded block RAMs, universal
programmable phase-locked loops, and the addition of
highly tuned networking specic phase-locked loops.
These functional blocks allow for easy glueless system
interfacing and the capability to adjust to varying condi-
tions in today’s high-speed networking systems.
Microprocessor Interface
The MPI provides a glueless interface between the
FPGA and PowerPC microprocessors. Programmable
in 8-, 16-, and 32-bit interfaces with optional parity to
the Motorola PowerPC 860 bus, it can be used for
conguration and readback, as well as for FPGA con-
trol and monitoring of FPGA status. All MPI transac-
tions utilize the Series 4 embedded system bus at
66 MHz performance.
A system-level microprocessor interface to the FPGA
user-dened logic following conguration, through the
system bus, including access to the embedded block
RAM and general user-logic, is provided by the MPI.
The MPI supports burst data read and write transfers,
allowing short, uneven transmission of data through the
interface by including data FIFOs. Transfer accesses
can be single beat (1 x 4 bytes or less), 4-beat (4 x
4 bytes), 8-beat (8 x 2 bytes), or 16-beat (16 x 1 bytes).
System Bus
An on-chip, multimaster, 8-bit system bus with 1-bit
parity facilitates communication among the MPI, con-
guration logic, FPGA control, and status registers,
embedded block RAMs, as well as user logic. Utilizing
the AMBA specication Rev 2.0 AHB protocol, the
embedded system bus offers arbiter, decoder, master,
and slave elements. Master and slave elements are
also available for the user-logic and a slave interface is
used for control and status of the embedded backplane
transceiver portion of the ORT82G5.
The system bus control registers can provide control to
the FPGA such as signaling for reprogramming, reset
functions, and PLL programming. Status registers
monitor INIT, DONE, and system bus errors. An inter-
rupt controller is integrated to provide up to eight possi-
ble interrupt resources. Bus clock generation can be
sourced from the microprocessor interface clock, con-
guration clock (for slave conguration modes), internal
oscillator, user clock from routing, or from the port clock
(for JTAG conguration modes).
Phase-Locked Loops
Up to eight PLLs are provided on each Series 4 device,
with four PLLs generally provided for FPSCs. Program-
mable PLLs can be used to manipulate the frequency,
phase, and duty cycle of a clock signal. Each PPLL is
capable of manipulating and conditioning clocks from
20 MHz to 420 MHz. Frequencies can be adjusted from
1/8x to 8x, the input clock frequency. Each programma-
ble PLL provides two outputs that have different multi-
plication factors but can have the same phase
relationships. Duty cycles and phase delays can be
adjusted in 12.5% of the clock period increments. An
automatic input buffer delay compensation mode is
available for phase delay. Each PPLL provides two out-
puts that can have programmable (12.5% steps) phase
differences.
Additional highly tuned and characterized, dedicated
phase-locked loops (DPLLs) are included to ease sys-
tem designs. These DPLLs meet ITU-T G.811 primary-
clocking specications and enable system designers to
very tightly target specied clock conditioning not tradi-
tionally available in the universal PPLLs. Initial DPLLs
are targeted to low-speed networking DS1 and E1, and
also high-speed SONET/SDH networking STS-3 and
STM-1 systems. These DPLLs are not typically
included on FPSC devices and are not found on the
ORT82G5.
Embedded Block RAM
New 512 x 18 quad-port RAM blocks are embedded in
the FPGA core to signicantly increase the amount of
memory and complement the distributed PFU memo-
ries. The EBRs include two write ports, two read ports,
and two byte lane enables which provide four-port
operation. Optional arbitration between the two write
ports is available, as well as direct connection to the
high-speed system bus.
Additional logic has been incorporated to allow signi-
cant exibility for FIFO, constant multiply, and two-vari-
able multiply functions. The user can congure FIFO
blocks with exible depths of 512k, 256k, and 1k includ-
ing asynchronous and synchronous modes and pro-
grammable status and error ags. Multiplier capabilities
allow a multiple of an 8-bit number with a 16-bit xed
coefcient or vice versa (24-bit output), or a multiply of
two 8-bit numbers (16-bit output). On-the-y coefcient
modications are available through the second read/
write port. Two 16 x 8-bit CAMs per embedded block
can be implemented in single match, multiple match,
and clear modes. The EBRs can also be preloaded at
device conguration time.
相关PDF资料 |
PDF描述 |
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| ORT82G5-3BM680 | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| OS10040280G-012 | FIBER OPTIC RECEIVER, 1290-1600nm, PANEL MOUNT, FC/APC CONNECTOR |
| OT-WBSC-Y-A-10-X-9-M-3-05-FA | FIBER OPTIC SPLITTER/COUPLER, 1X2PORT, 10.0, PANEL MOUNT, FC/APC CONNECTOR |
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| OT-WBSC-Y-A-50-X-9-O-1-99-SA | FIBER OPTIC SPLITTER/COUPLER, 1X2PORT, 50.0, PANEL MOUNT, SC/APC CONNECTOR |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ORT82G5-2BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2F680C | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2F680I | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORT82G5-2FN680C | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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