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参数资料
| 型号： | S29XS064R0PBHW010 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 80 ns, PBGA44 |
| 封装： | 7.50 X 5 MM, LEAD FREE, FBGA-44 |
| 文件页数： | 11/65页 |
| 文件大小： | 2116K |
| 代理商： | S29XS064R0PBHW010 |
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July 22, 2011 S29VS_XS064R_00_06
S29VS/XS-R MirrorBit
Flash Family
19
Da ta
Sh e e t
(Adv a n ce
In f o r m ation)
9.3.2
S29XS-R AADM Access
To burst read data from the memory array in AADM mode, the system must assert CE# to VIL, OE# must go
low with AVD# for one cycle while the upper address is valid. The rising edge of CLK when OE# and AVD#
are Low captures the upper 16 bits of address. The rising edge of CLK when OE# is High and AVD# is Low
latches the lower 16 bits of address. The data appears on A/DQ15 -A/DQ0 when CE# remains Low, after
OE# is Low and the synchronous access times are satisfied. The next data in the burst sequence is read on
each clock cycle that OE# and CE# remain Low.
Once OE# returns to VIH during a burst read the OE# no longer enables the outputs until after AVD# is at VIL
with OE# at VIH - which signals that address-low has been captured for the next burst access. This is so that
OE# at VIL may be used in conjunction with AVD# at VIL to indicate address-high on the A/DQ signals without
enabling the A/DQ outputs, thus avoiding data output contention with Address-high.
The device has a fixed internal address boundary that occurs every 128 words. A boundary crossing of one or
two additional wait states is required. The time the device is outputting data with the starting burst address not
divisible by eight, additional waits might be required.
The following Tables show the latency for variable wait state operation (note that ws = wait state).
Table 9.2 Wait State vs. Frequency
Wait State
Frequency (Maximum MHz)
3
27
4
40
5
54
6
66
7
80
8
95
9
108
Table 9.3 Address Latency for 10 -13 Wait States
Word
Initial Wait
Subsequent Clock Cycles After Initial Wait States
0
10 -13 wait states
D0
D1
D2
D3
D4
D5
D6
D7
+2 ws
D8
1
D1
D2
D3D4D5D6D7
1 ws
+2 ws
D8
2
D2
D3
D4D5D6D7
1 ws
+2 ws
D8
3
D3
D4
D5
D6
D7
1 ws
+2 ws
D8
4
D4
D5
D6
D7
1 ws
+2 ws
D8
5
D5
D6
D7
1 ws
+2 ws
D8
6
D6
D7
1 ws
+2 ws
D8
7
D7
1 ws
+2 ws
D8
Table 9.4 Address Latency for 9 Wait States
Word
Initial Wait
Subsequent Clock Cycles After Initial Wait States
0
9 wait states
D0
D1
D2
D3
D4
D5
D6
D7
+1 ws
D8
1
D1
D2
D3D4D5D6D7
1 ws
+1 ws
D8
2
D2
D3
D4D5D6D7
1 ws
+1 ws
D8
3
D3
D4
D5
D6
D7
1 ws
+1 ws
D8
4
D4
D5
D6
D7
1 ws
+1 ws
D8
5
D5
D6
D7
1 ws
+1 ws
D8
6
D6
D7
1 ws
+1 ws
D8
7
D7
1 ws
+1 ws
D8
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