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参数资料
| 型号： | S29XS064R0PBHW010 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 80 ns, PBGA44 |
| 封装： | 7.50 X 5 MM, LEAD FREE, FBGA-44 |
| 文件页数： | 18/65页 |
| 文件大小： | 2116K |
| 代理商： | S29XS064R0PBHW010 |
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July 22, 2011 S29VS_XS064R_00_06
S29VS/XS-R MirrorBit
Flash Family
25
Da ta
Sh e e t
(Adv a n ce
In f o r m ation)
9.16
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept commands on the
rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up
9.17
Lock Register
The Lock Register consists of one bit. This bit is non-volatile and read-only. DQ15-DQ1 are reserved and are
undefined.
Note
When the device lock register is programmed (the Secured Silicon lock bit is programmed) all DYBs revert to the power-on default state.
9.18
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state,
independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at VCC. The
device requires standard access time (tCE) for read access when the device is in either of these standby
modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation
is completed.
9.19
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enters this
mode when addresses and clock remain stable for tACC + 20 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses
are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in
Table 16.1, CMOS Compatible on page 52 represents the automatic sleep mode current specification.
Table 9.12 Lock Register
DQ15-1
DQ0
Undefined
Secured Silicon Sector Protection Bit
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