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参数资料
| 型号： | S29XS064R0PBHW010 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 80 ns, PBGA44 |
| 封装： | 7.50 X 5 MM, LEAD FREE, FBGA-44 |
| 文件页数： | 41/65页 |
| 文件大小： | 2116K |
| 代理商： | S29XS064R0PBHW010 |
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46
S29VS/XS-R MirrorBit
Flash Family
S29VS_XS064R_00_06 July 22, 2011
Data
Sheet
(Adv an ce
Inf o r m a t io n)
Figure 13.1 Data# Polling Algorithm
Notes
1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being
erased. During chip erase, a valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
13.2
RDY: Ready
The RDY pin is a dedicated status output that indicates valid output data on A/DQ15–A/DQ0 during burst
(synchronous) reads. When RDY is asserted (RDY = VOH), the output data is valid and can be read. When
RDY is de-asserted (RDY = VOL), the system should wait until RDY is re-asserted before expecting the next
word of data.
In synchronous (burst) mode with CE# = OE# = VIL, RDY is de-asserted under the following conditions:
during the initial access; after crossing the internal boundary between addresses 7Eh and 7Fh (and
addresses offset from these by a multiple of 64). The RDY pin will also switch during status reads when a
clock signal drives the CLK input. In addition, RDY = VOH when CE# = VIL and OE# = VIH, and RDY is Hi-Z
when CE# = VIH.
In asynchronous (non-burst) mode, the RDY pin does not indicate valid or invalid output data. Instead,
RDY = VOH when CE# = VIL, and RDY is Hi-Z when CE# = VIH.
DQ7 = Data?
Yes
No
DQ5 = 1?
No
Yes
FAIL
PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
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