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参数资料
| 型号： | S29XS064R0PBHW010 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 80 ns, PBGA44 |
| 封装： | 7.50 X 5 MM, LEAD FREE, FBGA-44 |
| 文件页数： | 29/65页 |
| 文件大小： | 2116K |
| 代理商： | S29XS064R0PBHW010 |
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July 22, 2011 S29VS_XS064R_00_06
S29VS/XS-R MirrorBit
Flash Family
35
Da ta
Sh e e t
(Adv a n ce
In f o r m ation)
12. Configuration Register
Table 12.1 shows the address bits that determine the configuration register settings for various device
functions.
Notes
1. Device will be in the default state upon power-up or hardware reset.
2. CR3 will always equal to 1 (Wrap around mode) when CR0,CR1,CR2 = 000 (continuous Burst mode).
12.1
Reset Command
Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t
cares for this command.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure
begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program command sequence before
programming begins. This resets the bank to which the system was writing to the read mode. If the program
command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command
returns that bank to the erase-suspend-read mode. Once programming begins, however, the device
ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank
entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank
to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the
read mode (or erase-suspend-read mode if that bank was in Erase Suspend).
Table 12.1 Configuration Register
CR BIt
Function
Settings (Binary)
CR15
Device Read
Mode
0 = Synchronous Read Mode
1 = Asynchronous Read Mode (Default)
CR14
Reserved
0 = Default
CR13
Programmable
Wait State
000 = Reserved
001 = Data is valid on the 3rd active CLK edge after addresses are latched
010 = Data is valid on the 4th active CLK edge after addresses are latched
011 = Data is valid on the 5th active CLK edge after addresses are latched
100 = Data is valid on the 6th active CLK edge after addresses are latched
101 = Data is valid on the 7th active CLK edge after addresses are latched (default)
110 = Data is valid on the 8th active CLK edge after addresses are latched
111 = Data is valid on the 9th active CLK edge after addresses are latched
CR12
CR11
CR10
RDY Polarity
0 = RDY signal is active low
1 = RDY signal is active high (default)
CR9
Reserved
1 = Default
CR8
RDY
0 = RDY active one clock cycle before data
1 = RDY active with data (default)
CR7
Reserved
1 = default
CR6
Reserved
1 = default
CR5
Reserved
0 = default
CR4
Reserved
0 = default
CR3
Burst Wrap
Around
0 = Reserved
1 = Wrap Around Burst (default)
CR2
Burst Length
000 = Continuous (default)
010 = 8-Word Linear Burst
011 = 16-Word Linear Burst
100 = Reserved
(All other bit settings are reserved)
CR1
CR0
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