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| 型号： | S29XS064R0PBHW010 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 80 ns, PBGA44 |
| 封装： | 7.50 X 5 MM, LEAD FREE, FBGA-44 |
| 文件页数： | 8/65页 |
| 文件大小： | 2116K |
| 代理商： | S29XS064R0PBHW010 |
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16
S29VS/XS-R MirrorBit
Flash Family
S29VS_XS064R_00_06 July 22, 2011
Data
Sheet
(Adv an ce
Inf o r m a t io n)
8.
Address/Data Configuration (Interface) Modes
There are two options for connection to the address and data buses.
Address and Data Multiplexed (ADM) mode - On the S29VS-R devices upper address is supplied on
separate signal inputs and the lower 16-bits of address are multiplexed with 16-bit data on the A/DQ15 to
A/DQ0 I/Os.
Address-high, Address-low, and Data Multiplexed (AADM) mode - On the S29XS-R devices upper and
lower address are multiplexed with 16-bit data on the A/DQ15 to A/D0 signal I/Os.
The two options allow use with the traditional address/data multiplexed NOR interface (S29VS family), or an
address multiplexed/data multiplexed interface with the lowest signal count (S29XS family).
ADM or AADM mode can be selected via ordering part number only.
8.1
ADM Interface Mode (S29VS064R)
In ADM mode, the AVD# signal is used to capture the entire address with a single toggle of AVD# in
asynchronous mode or in a single clock cycle in synchronous mode.
8.2
AADM Interface Mode (S29XS064R)
Signal input and output (I/O) connections on a high complexity component such as an Application Specific
Integrated Circuit (ASIC) are a limited resource. Reducing signal count on any interface of the ASIC allows for
either more features or lower package cost. The memory interface described in this section is intended to
reduce the I/O signal count associated with the Flash memory interface with an ASIC.
The interface is called Address-High, Address-Low, and Data Multiplexed (AADM) because all address and
data information is time multiplexed on a single 16-bit wide bus. This interface is electrically compatible with
existing ADM 16-bit wide random access static memory interfaces but uses fewer address signals. In that
sense AADM is a signal count subset of existing static memory interfaces. This interface can be implemented
in existing memory controller designs, as an additional mode, with minimal changes. No new
I/O technology is needed and existing memory interfaces can continue to be supported while the electronics
industry adopts this new interface. ASIC designers can reuse the existing memory address signals above
A15 for other functions when an AADM memory is in use.
By breaking up the memory address in to two time slots the address is naturally extended to be a 32-bit word
address. But, using two bus cycles to transfer the address increases initial access latency by increasing the
time address is using the bus. However, many memory accesses are to locations in memory nearby the
previous access. Very often it is not necessary to provide both cycles of address. This interface stores the
high half of address in the memory so that if the high half of address does not change from the previous
access, only the low half of address needs to be sent on the bus. If a new upper address is not captured at
the beginning of an access the last captured value of the upper address is used. This allows accesses within
the same 128-KByte address range to provide only the lower address as part of each access.
In AADM mode two signal rising edges are needed to capture the upper and lower address portions in
asynchronous mode or two signal combinations over two clocks is needed in synchronous mode. In
asynchronous mode the upper address is captured by an AVD# rising edge when OE# is Low; the lower
address is captured on the rising edge of AVD# with OE# High. In synchronous mode the upper address is
captured at the rising clock edge when AVD# and OE# are Low; the lower address is captured at the rising
edge of clock when AVD# is Low and OE# is High.
CE# going High at any time during the access or OE# returning High after RDY is first asserted High during
an access, terminates the read access and causes the address/data bus direction to switch back to input
mode. The address/data bus direction switches from input to output mode only after an Address-Low capture
when AVD# is Low and OE# is High. This prevents the assertion of OE# during Address-High capture from
causing a bus conflict between the host address and memory data signals. Note, in burst mode, this implies
at least one cycle of CE# or OE# High before an Address-high for a new access may be placed on the bus so
that there is time for the memory to recognize the end of the previous access, stop driving data outputs, and
ignore OE# so that assertion of OE# with the new Address-high does not create a bus conflict with a new
address being driven on the bus. At high bus frequencies more than one cycle may be need in order to allow
time for data outputs to stop driving and new address to be driven (bus turn around time).
During a write access, the address/data bus direction is always in the input mode.
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