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参数资料
| 型号： | S29XS064R0PBHW010 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 80 ns, PBGA44 |
| 封装： | 7.50 X 5 MM, LEAD FREE, FBGA-44 |
| 文件页数： | 35/65页 |
| 文件大小： | 2116K |
| 代理商： | S29XS064R0PBHW010 |
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40
S29VS/XS-R MirrorBit
Flash Family
S29VS_XS064R_00_06 July 22, 2011
Data
Sheet
(Adv an ce
Inf o r m a t io n)
12.7
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical erase. The system is not required to provide any
controls or timings during these operations. Table 12.3 on page 43 shows the address and data requirements
for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no
longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. Refer
to Write Operation Status on page 45 for information on these status bits.
Any commands written during the chip erase operation are ignored. However, note that a hardware reset
immediately terminates the erase operation. If that occurs, the chip erase command sequence should be
reinitiated once that bank has returned to reading array data, to ensure data integrity.
12.8
Sector Erase Command Sequence
Sector erase in normal mode is a six bus cycle operation. The sector erase command sequence is initiated by
writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are
then followed by the address of the sector to be erased, and the sector erase command. Table 12.3
on page 43 shows the address and data requirements for the sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase.
The system is not required to provide any controls or timings during these operations.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3:
Sector Erase start timeout state indicator.). The time-out begins from the rising edge of the final WE# pulse in
the command sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are
no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data
from the non-erasing banks. The system can determine the status of the erase operation by reading DQ7 or
DQ6/ DQ2 in the erasing bank. Refer to Write Operation Status on page 45 for information on these status
bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands
are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs,
the sector erase command sequence should be reinitiated once that bank has returned to reading array data,
to ensure data integrity.
Accelerated Sector Erase
The device offers accelerated sector erase operation through the VPP function. This method of erasing
sectors is faster than the standard sector erase command sequence. The accelerated sector erase
function must not be used more than 100 times per sector. In addition, accelerated sector erase should
be performed at room temperature (30
C ±10C).
The following procedure is used to perform accelerated sector erase:
1. Sectors to be erased must be DYB cleared. All sectors that remain locked will not be erased.
3. Issue the standard chip erase command.
4. Monitor status bits DQ2/DQ6 or DQ7 to determine when erasure is complete, just as in the
standard erase operation. See Write Operation Status on page 45 for further details.
5. Lower VPP from 9V to VCC.
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