参数资料
型号: W9725G6JB25I
厂商: Winbond Electronics
文件页数: 2/87页
文件大小: 0K
描述: IC DDR2 SDRAM 256MBIT 84WBGA
标准包装: 200
格式 - 存储器: RAM
存储器类型: DDR2 SDRAM
存储容量: 256M(16Mx16)
速度: 2.5ns
接口: 并联
电源电压: 1.7 V ~ 1.9 V
工作温度: -40°C ~ 95°C
封装/外壳: 84-TFBGA
供应商设备封装: 84-WBGA(8x12.5)
包装: 托盘
W9725G6JB
7.4.2
7.4.3
7.4.4
7.4.5
Burst mode operation ....................................................................................................... 24
Burst read mode operation ............................................................................................... 25
Burst write mode operation .............................................................................................. 25
Write data mask ............................................................................................................... 26
7.5
7.6
Burst Interrupt ..................................................................................................................................... 26
Precharge operation............................................................................................................................ 27
7.6.1
7.6.2
Burst read operation followed by precharge ..................................................................... 27
Burst write operation followed by precharge .................................................................... 27
7.7
Auto-precharge operation ................................................................................................................... 27
7.7.1
7.7.2
Burst read with Auto-precharge ....................................................................................... 28
Burst write with Auto-precharge ....................................................................................... 28
7.8
7.9
Refresh Operation ............................................................................................................................... 29
Power Down Mode .............................................................................................................................. 29
7.9.1
7.9.2
Power Down Entry ........................................................................................................... 30
Power Down Exit .............................................................................................................. 30
8.
9.
7.10
8.1
8.2
8.3
8.4
8.5
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
Input clock frequency change during precharge power down ............................................................. 30
OPERATION MODE ........................................................................................................................... 31
Command Truth Table ........................................................................................................................ 31
Clock Enable (CKE) Truth Table for Synchronous Transitions ........................................................... 32
Data Mask (DM) Truth Table ............................................................................................................... 32
Function Truth Table ........................................................................................................................... 33
Simplified Stated Diagram ................................................................................................................... 36
ELECTRICAL CHARACTERISTICS ................................................................................................... 37
Absolute Maximum Ratings ................................................................................................................ 37
Operating Temperature Condition ....................................................................................................... 37
Recommended DC Operating Conditions ........................................................................................... 38
ODT DC Electrical Characteristics ...................................................................................................... 38
Input DC Logic Level ........................................................................................................................... 38
Input AC Logic Level ........................................................................................................................... 38
Capacitance ........................................................................................................................................ 39
Leakage and Output Buffer Characteristics ........................................................................................ 39
DC Characteristics .............................................................................................................................. 40
IDD Measurement Test Parameters.................................................................................................... 42
AC Characteristics .............................................................................................................................. 43
9.11.1
9.11.2
AC Characteristics and Operating Condition for -18 speed grade ................................... 43
AC Characteristics and Operating Condition for -25/25I/25A/25K/-3 speed grade ........... 45
9.12
9.13
9.14
AC Input Test Conditions .................................................................................................................... 66
Differential Input/Output AC Logic Levels ........................................................................................... 66
AC Overshoot / Undershoot Specification ........................................................................................... 67
9.14.1
9.14.2
AC Overshoot / Undershoot Specification for Address and Control Pins: ........................ 67
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask pins: .......... 67
10.
10.1
TIMING WAVEFORMS ....................................................................................................................... 68
Command Input Timing ....................................................................................................................... 68
Publication Release Date: Nov. 29, 2011
-2-
Revision A02
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