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| 型号： | W9725G6JB25I |
| 厂商： | Winbond Electronics |
| 文件页数： | 61/87页 |
| 文件大小： | 0K |
| 描述： | IC DDR2 SDRAM 256MBIT 84WBGA |
| 标准包装： | 200 |
| 格式 - 存储器： | RAM |
| 存储器类型： | DDR2 SDRAM |
| 存储容量： | 256M（16Mx16） |
| 速度： | 2.5ns |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.9 V |
| 工作温度： | -40°C ~ 95°C |
| 封装/外壳： | 84-TFBGA |
| 供应商设备封装： | 84-WBGA（8x12.5） |
| 包装： | 托盘 |
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W9725G6JB
45. Slew Rate Measurement Levels:
a)
Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended
signals.
For differential signals (e.g. DQS - DQS ) output slew rate is measured between DQS - DQS = - 500 mV and DQS - DQS
= + 500 mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device.
b) Input slew rate for single ended signals is measured from VREF(dc) to VIH(ac),min for rising edges and from VREF(dc) to
VIL(ac),max for falling edges.
For differential signals (e.g. CLK - CLK ) slew rate for rising edges is measured from CLK - CLK = - 250 mV to CLK -
CLK = + 500 mV (+ 250 mV to - 500 mV for falling edges).
c) V ID is the magnitude of the difference between the input voltage on CLK and the input voltage on CLK , or between DQS
and DQS for differential strobe.
46. DDR2 SDRAM output slew rate test load:
Output slew rate is characterized under the test conditions as shown in below figure.
VDDQ
DQ
DUT
DQS, DQS
Output
Test point
25 Ω
VTT = VDDQ/2
Output slew rate test load
47. Differential data strobe:
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS
“Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2
SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the
rising or falling edges of DQS crossing at V REF . In differential mode, these timing relationships are measured relative to the
cross point of DQS and its complement, DQS . This distinction in timing methods is guaranteed by design and characterization.
Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS , must be tied externally
to VSS thro ugh a 20 Ω to 10 kΩ resistor to insure proper operation.
Publication Release Date: Nov. 29, 2011
- 61 -
Revision A02
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W9725G6KB-18 | 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W9725G6KB-25 | 功能描述:IC DDR2 SDRAM 256MBIT 84WBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:4G（256M x 16） 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP I 包装:Digi-Reel® 其它名称:557-1461-6 |
| W9725G6KB-25 TR | 制造商:Winbond Electronics Corp 功能描述:256M DDR2-800, X16 |
| W9725G6KB25A | 制造商:WINBOND 制造商全称:Winbond 功能描述:DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask |
| W9725G6KB25I | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 256M-Bit 16Mx16 1.8V 84-Pin WBGA 制造商:Winbond Electronics 功能描述:IC DDR2 SDRAM 256M 2.5NS 84WBGA 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 256M 2.5NS 84WBGA 制造商:Winbond 功能描述:DRAM Chip DDR2 SDRAM 256M-Bit 16Mx16 1.8V 84-Pin WBGA |
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