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| 型号： | W9725G6JB25I |
| 厂商： | Winbond Electronics |
| 文件页数： | 55/87页 |
| 文件大小： | 0K |
| 描述： | IC DDR2 SDRAM 256MBIT 84WBGA |
| 标准包装： | 200 |
| 格式 - 存储器： | RAM |
| 存储器类型： | DDR2 SDRAM |
| 存储容量： | 256M（16Mx16） |
| 速度： | 2.5ns |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.9 V |
| 工作温度： | -40°C ~ 95°C |
| 封装/外壳： | 84-TFBGA |
| 供应商设备封装： | 84-WBGA（8x12.5） |
| 包装： | 托盘 |
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W9725G6JB
43. tIS and tIH (input setup and hold) derating.
tIS/tIH Derating values for DDR2-667, DDR2-800 and DDR2-1066
ΔtIS and ΔtIH Derating Values for DDR2 -667, DDR2-800 and DDR2-1066
Command/
Address
CLK/ CLK Differential Slew Rate
Slew Rate
(V/nS)
ΔtIS
2.0 V/nS
ΔtI H
ΔtIS
1.5 V/nS
ΔtI H
ΔtIS
1.0 V/nS
ΔtI H
Unit
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
+150
+143
+133
+120
+100
+67
0
-5
-13
-22
-34
-60
-100
-168
-200
-325
-517
-1000
+94
+89
+83
+75
+45
+21
0
-14
-31
-54
-83
-125
-188
-292
-375
-500
-708
-1125
+180
+173
+163
+150
+130
+97
+30
+25
+17
+8
-4
-30
-70
-138
-170
-295
-487
-970
+124
+119
+113
+105
+75
+51
+30
+16
-1
-24
-53
-95
-158
-262
-345
-470
-678
-1095
+210
+203
+193
+180
+160
+127
+60
+55
+47
+38
+26
0
-40
-108
-140
-265
-457
-940
+154
+149
+143
+135
+105
+81
+60
+46
+29
+6
-23
-65
-128
-232
-315
-440
-648
-1065
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and
tIH(base) value to the ΔtIS and ΔtIH derating value respectively. Example: tIS (total setup time) = tIS(base) + ΔtI S.
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first
crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line between
shaded ?VREF(dc) to AC region?, use nominal slew rate for derating value . See Figure 20 Illustration of nominal slew rate for tIS.
If the actual signal is later than the nominal slew rate line anywhere between shad ed ?VREF(dc) to AC region?, the slew rate of a
tangent line to the actual signal from the AC level to DC level is used for derating value. See Figure 21 Illustration of tangent line
for tIS.
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first
crossing of VREF(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
VIH(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between
shaded ? DC to VREF(dc) region?, use nominal slew rate for derating value . See Figure 22 Illustration of nominal slew rate for tIH.
If the actual signal is earlier than the nominal slew rate line anywhere between shaded ? DC to VREF(dc) region?, the slew rate of
a tangent line to the actual signal from the DC level to VREF(dc) level is used for derating value. See Figure 23 Illustration of
tangent line for tIH.
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at
the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rates in between the values listed in above tIS/tIH derating values for DDR2-667, DDR2-800 and DDR2-1066 table, the
derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
Publication Release Date: Nov. 29, 2011
- 55 -
Revision A02
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W9725G6KB-18 | 制造商:Winbond Electronics 功能描述:IC MEMORY 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W9725G6KB-25 | 功能描述:IC DDR2 SDRAM 256MBIT 84WBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:4G（256M x 16） 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP I 包装:Digi-Reel® 其它名称:557-1461-6 |
| W9725G6KB-25 TR | 制造商:Winbond Electronics Corp 功能描述:256M DDR2-800, X16 |
| W9725G6KB25A | 制造商:WINBOND 制造商全称:Winbond 功能描述:DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask |
| W9725G6KB25I | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 256M-Bit 16Mx16 1.8V 84-Pin WBGA 制造商:Winbond Electronics 功能描述:IC DDR2 SDRAM 256M 2.5NS 84WBGA 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 256M 2.5NS 84WBGA 制造商:Winbond 功能描述:DRAM Chip DDR2 SDRAM 256M-Bit 16Mx16 1.8V 84-Pin WBGA |
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