参数资料
型号: W9725G6JB25I
厂商: Winbond Electronics
文件页数: 66/87页
文件大小: 0K
描述: IC DDR2 SDRAM 256MBIT 84WBGA
标准包装: 200
格式 - 存储器: RAM
存储器类型: DDR2 SDRAM
存储容量: 256M(16Mx16)
速度: 2.5ns
接口: 并联
电源电压: 1.7 V ~ 1.9 V
工作温度: -40°C ~ 95°C
封装/外壳: 84-TFBGA
供应商设备封装: 84-WBGA(8x12.5)
包装: 托盘
W9725G6JB
9.12 AC Input Test Conditions
CONDITION
Input reference voltage
Input signal maximum peak to peak swing
Input signal minimum slew rate
SYMBOL
V REF
V SWING(MAX)
SLEW
VALUE
0.5 x V DDQ
1.0
1.0
UNIT
V
V
V/nS
NOTES
1
1
2, 3
Notes:
1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(ac) level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the
range from VREF to VIL(ac) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to
VIL(ac) on the negative transitions.
9.13 Differential Input/Output AC Logic Levels
PARAMETER
AC differential input voltage
AC differential cross point input voltage
AC differential cross point output voltage
SYM.
V ID (ac)
V IX (ac)
V OX (ac)
MIN.
0.5
0.5 x VDDQ - 0.175
0.5 x VDDQ - 0.125
MAX.
VDDQ + 0.6
0.5 x VDDQ + 0.175
0.5 x VDDQ + 0.125
UNIT
V
V
V
NOTES
1
2
3
Notes:
1. VID (ac) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such
as CLK, LDQS or UDQS) and VCP is the complementary input signal (such as CLK , LDQS or UDQS ). The minimum
value is equal to VIH (ac) - VIL (ac).
2. The typical value of VIX (ac) is expected to be about 0.5 x VDDQ of the transmitting device and VIX (ac) is expected to track
variations in VDDQ. VIX (ac) indicates the voltage at which differential input signals must cross.
3. The typical value of VOX (ac) is expected to be about 0.5 x VDDQ of the transmitting device and VOX (ac) is expected to
track variations in VDDQ. VOX (ac) indicates the voltage at which differential output signals must cross.
V DDQ
V IH(ac) min
V IH(dc) min
V SWING(MAX)
V REF
V IL(dc) max
V TR
V DDQ
V IL(ac) max
V SS
V CP
V ID
Crossing point
V IX or V OX
Δ TF
Δ TR
V SSQ
Falling Slew =
V REF - V IL(ac) max
Δ TF
Rising Slew =
V IH(ac) min - V REF
Δ TR
Figure 28 – AC input test signal and Differential signal levels waveform
Publication Release Date: Nov. 29, 2011
- 66 -
Revision A02
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