参数资料
型号: W9725G6JB25I
厂商: Winbond Electronics
文件页数: 40/87页
文件大小: 0K
描述: IC DDR2 SDRAM 256MBIT 84WBGA
标准包装: 200
格式 - 存储器: RAM
存储器类型: DDR2 SDRAM
存储容量: 256M(16Mx16)
速度: 2.5ns
接口: 并联
电源电压: 1.7 V ~ 1.9 V
工作温度: -40°C ~ 95°C
封装/外壳: 84-TFBGA
供应商设备封装: 84-WBGA(8x12.5)
包装: 托盘
W9725G6JB
9.9
DC Characteristics
-18
-25/25I/25A/25K
-3
SYM.
CONDITIONS
MAX.
MAX.
MAX.
UNIT
NOTES
Operating Current - One Bank Active-Precharge
I DD0
t CK = t CK(IDD) , t RC = t RC(IDD) , t RAS = t RASmin(IDD) ;
CKE is HIGH, CS is HIGH between valid commands;
Address and control inputs are SWITCHING;
70
60
55
mA
1,2,3,4,5,
6
Databus inputs are SWITCHING.
Operating Current - One Bank Active-Read-
Precharge
I OUT = 0 mA;
BL = 4, CL = CL (IDD) , AL = 0;
I DD1
t CK = t CK(IDD) , t RC = t RC(IDD) , t RAS = t RASmin(IDD) ,
t RCD = t RCD(IDD) ;
80
70
65
mA
1,2,3,4,5,
6
CKE is HIGH, CS is HIGH between valid commands;
Address and control inputs are SWITCHING;
Data bus inputs are SWITCHING.
Precharge Power-Down Current
All banks idle;
I DD2P
t CK = t CK(IDD) ;
CKE is LOW;
6
6
6
mA
1,2,3,4,5,
6,7
Other control and address inputs are STABLE;
Data Bus inputs are FLOATING. (T CASE ≤ 85°C)
Precharge Standby Current
All banks idle;
I DD2N
t CK = t CK(IDD) ;
CKE is HIGH, CS is HIGH;
45
40
35
mA
1,2,3,4,5,
6
Other control and address inputs are SWITCHING;
Data bus inputs are SWITCHING.
Precharge Quiet Standby Current
All banks idle;
I DD2Q
t CK = t CK(IDD) ;
CKE is HIGH, CS is HIGH;
35
35
30
mA
1,2,3,4,5,
6
Other control and address inputs are STABLE;
Data bus inputs are FLOATING.
I DD3PF
Active Power-Down Current
All banks open;
t CK = t CK(IDD) ;
Fast PDN Exit
MRS(12) = 0
15
15
15
mA
1,2,3,4,5,
6
CKE is LOW;
Other control and address inputs are
I DD3PS
STABLE;
Data bus inputs are FLOATING.
Slow PDN Exit
MRS(12) = 1
10
10
10
mA
1,2,3,4,5,
6,7
(T CASE ≤ 85°C)
Active Standby Current
All banks open;
I DD3N
t CK = t CK(IDD) ; t RAS = t RASmax(IDD) , t RP = t RP(IDD) ;
CKE is HIGH, CS is HIGH between valid commands;
60
50
45
mA
1,2,3,4,5,
6
Other control and address inputs are SWITCHING;
Data bus inputs are SWITCHING.
Publication Release Date: Nov. 29, 2011
- 40 -
Revision A02
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