80
Datasheet
Features
The processor SMBus implementation uses the clock and data signals of the V1.1 System
Management Bus Specification. It does not implement the SMBSUS# signal. Layout and routing
guidelines are available in the appropriate platform design guidelines document and the SMBus
and I2C Bus Design Guide application note.
For platforms which do not implement any of the SMBus features found on the processor, all of the
SMBus connections,
except SM_VCC, to the socket pins may be left unconnected (SM_ALERT#,
SM_CLK, SM_DAT, SM_EP_A[2:0], SM_TS_A[1:0], SM_WP). SM_VCC provides power to the
VID generation logic in addition to supplying the SMBus and must be supplied with 3.3 volt power
to assure correct setting of the processor core voltage (V
CC).
NOTE: Actual implementation may vary. For use in general understanding of the architecture. All SMBus pull-up
and pull-down resistors are 10K
and located on the processor.
6.4.1
Processor Information ROM (PIROM)
The lower half (128 bytes) of the SMBus memory component is an electrically programmed read-
only memory with information about the processor. This information is permanently write-
protected.
Table 35 shows the data fields and formats provided in the Processor Information ROM
(PIROM).
Figure 42. Logical Schematic of SMBus Circuitry
SM_EP_A1
Processor
Information
ROM
and
Scratch
EEPROM
(1 Kbit each)
Thermal
Sensor
A0
A1
A2
WP
A0
A1
SM_EP_A0
SM_EP_A2
SM_TS_A0
SM_TS_A1
SM_VCC
CLK
DATA
VCC
VSS
STDBY#
ALERT#
SM_CLK
SM_DAT
SM_ALERT#
SM_WP
Table 35. Processor Information ROM Format (Sheet 1 of 3)
Offset/Section
# of
Bits
Function
Notes
Header:
00h
8
Data Format Revision
Two 4-bit hex digits
01 - 02h
16
EEPROM Size
Size in bytes (MSB first)