48
Datasheet
System Bus Signal Quality Specifications
3.2
System Bus Signal Quality Specifications and
Measurement Guidelines
Many scenarios have been simulated to generate a set of AGTL+ layout guidelines which are
available in the appropriate platform design guidelines.
Table 23 provides the signal quality specifications for all processor signals for use in simulating
signal quality at the processor pads.
Intel Xeon processor MP on the 0.13 micron process processor maximum allowable overshoot and
undershoot specifications for a given duration of time are detailed in
Table 25 through
Table 28.
Figure 21 shows the system bus ringback tolerance for low-to-high transitions and
Figure 22 shows
ringback tolerance for high-to-low transitions.
NOTES:
1. All signal integrity specifications are measured at the processor core (pads).
2. Unless otherwise noted, all specifications in this table apply to all Intel Xeon processor MP on the 0.13 micron
process processor frequencies and cache sizes.
3. Specifications are for the edge rate of 0.3 - 4.0 V/ns at the receiver.
4. All values specified by design characterization.
5. Please see
Section 3.1 for maximum allowable overshoot.
6. Intel recommends simulations not exceed a ringback value of GTLREF ± 0.100*GTLREF to allow margin for
other sources of system noise.
Figure 20. BCLK[1:0] Signal Integrity Waveform
Crossing
Voltage
Threshold
Region
VH
VL
Overshoot
Undershoot
Ringback
Margin
Rising Edge
Ringback
Falling Edge
Ringback,
BCLK0
BCLK1
Crossing
Voltage
Table 23. Ringback Specifications for AGTL+ and Asynchronous GTL+ Buffers
Signal Group
Transition
Maximum Ringback
(with Input Diodes Present)
Unit
Figure
Notes
AGTL+, Asynch GTL+
L
→ H
GTLREF + 0.100*GTLREF
V
1, 2, 3, 4, 5, 6
AGTL+, Asynch GTL+
H
→ L
GTLREF - 0.100*GTLREF
V
1, 2, 3, 4, 5, 6