Datasheet
23
Electrical Specifications
the rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and can
become active at any time during the clock cycle.
Table 5 identifies which signals are common
clock, source synchronous and asynchronous.
NOTES:
2. These signal groups are not terminated by the processor.
3. These signals do not have on-die termination. Refer to corresponding platform design guidelines for
termination requirements.
4. Note that Reset initialization function of these pins is now a software function on the Intel Xeon
processor MP on the 0.13 micron process processor.
5. The value of these pins during the active-to-inactive edge of RESET# to determine processor configuration
6. These signals may be driven simultaneously by multiple agents (wired-or).
7. These signals are not terminated by the processor’s on-die termination. However, some signals in this group
include termination on the processor interposer. See
Section 6.4 for details.
8. SM_Vcc is required for correct operation of the Intel Xeon processor MP on the 0.13 micron process
processors VID logic. Refer to
Figure 18 for details.
Table 5. System Bus Signal Groups
Signal Group
Type
Signals 1
AGTL+ Common Clock Input
Synchronous to BCLK[1:0]
BPRI#, BR[3:1]#3, DEFER#, RESET#3,
RS[2:0]#, RSP#, TRDY#
AGTL+ Common Clock I/O
Synchronous to BCLK[1:0]
ADS#, AP[1:0]#, BINIT#6, BNR#6,
BPM[5:0]#2, BR0#2, DBSY#, DP[3:0]#,
DRDY#, HIT#6, HITM#6, LOCK#, MCERR#6
AGTL+ Source Synchronous
I/O
Synchronous to assoc.
strobe
AGTL+ Strobes
Synchronous to BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
Asynchronous GTL+ Input 3
Asynchronous
A20M#4, IGNNE#4, INIT#5, LINT0/INTR4,
LINT1/NMI4, SMI#5, SLP#, STPCLK#
Asynchronous GTL+ Output 3
Asynchronous
FERR#, IERR#, THERMTRIP#, PROCHOT#
System Bus Clock
Clock
BCLK1, BCLK0
TAP Input 2
Synchronous to TCK
TCK, TDI, TMS, TRST#
TAP Output 2
Synchronous to TCK
TDO
SMBus Interface 7
Synchronous to SM_CLK
SM_EP_A[2:0], SM_TS_A[1:0], SM_DAT,
SM_CLK, SM_ALERT#, SM_WP
Power/Other
BSEL[1:0], COMP[1:0], GTLREF, ODTEN,
PWRGOOD, Reserved, SKTOCC#,
TESTHI[6:0],VID[4:0], VCC, SM_VCC8, VCCA ,
VCCIOPLL, VSSA, , VSS, VCCSENSE, VSSSENSE
Signals
Associated Strobe
REQ[4:0]#,A[16:3]#5
ADSTB0#
A[35:17]#4
ADSTB1#
D[15:0]#, DBI0#
DSTBP0#, DSTBN0#
D[31:16]#, DBI1#
DSTBP1#, DSTBN1#
D[47:32]#, DBI2#
DSTBP2#, DSTBN2#
D[63:48]#, DBI3#
DSTBP3#, DSTBN3#