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参数资料
| 型号： | YF80532KC0211M |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1500 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | MICRO, PGA-603 |
| 文件页数： | 37/129页 |
| 文件大小： | 1528K |
| 代理商： | YF80532KC0211M |
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Datasheet
15
Electrical Specifications
2
2.1
System Bus and GTLREF
Most Xeon processor family system bus signals use Assisted Gunning Transceiver Logic (AGTL+)
signaling technology. This signaling technology provides improved noise margins and reduced
ringing through low voltage swings and controlled edge rates. The termination voltage level for the
Xeon processor family AGTL+ signals is VCC, the operating voltage of the processor core. This is
the same as the previous Intel Xeon processor MP processor. VTT (termination voltage level for the
I/O buffers) is identical to VCC on the Intel Xeon processor family. The use of a termination voltage
that is determined by the processor core allows better voltage scaling on the system bus for the
Intel Xeon processor MP on the 0.13 micron process. Because of the speed improvements to data
and address busses, signal integrity and platform design methods become more critical than with
previous processor families. Design guidelines for the Intel Xeon processor MP on the 0.13 micron
process system bus are detailed in the appropriate platform design guide (refer to Section 1.2).
The AGTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the baseboard (See
Table 14 for GTLREF specifications). Termination resistors are provided on the processor silicon
and are terminated to its core voltage (VCC). The on-die termination resistors are a selectable
feature and can be enabled or disabled via the ODTEN pin. For end bus agents, on-die termination
can be enabled to control reflections on the transmission line. For middle bus agents, on-die
termination must be disabled. Intel chipsets will also provide on-die termination, thus eliminating
the need to terminate the bus on the baseboard for most AGTL+ signals. Refer to Section 2.12 for
details on ODTEN resistor termination requirements.
Note: Some AGTL+ signals do not include on-die termination and must be terminated on the baseboard.
See Table 5 for details regarding these signals.
The AGTL+ signals depend on incident wave switching. Therefore timing calculations for AGTL+
signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the
system bus, including trace lengths, is highly recommended when designing a system. The Intel
Xeon Processor MP on the 0.13 Micron Process Processor Signal Integrity and Package Models
are available through your Intel representative.
2.2
Power and Ground Pins
For clean on-chip power distribution, Intel Xeon processor MP on the 0.13 micron process
processor has 190 VCC (power) and 189 VSS (ground) inputs. All power pins must be connected to
the system power plane, while all VSS pins must be connected to the system ground plane. The
processor VCC pins must be supplied the voltage determined by the processor VID (Voltage ID)
pins.
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相关代理商/技术参数 |
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| YFA014C049ZA | 制造商:Panasonic Industrial Company 功能描述:CHASSIS |
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| YFAW025 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
| YFAW025-02 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
| YFAW025-03 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
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