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参数资料
| 型号： | YF80532KC0211M |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1500 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | MICRO, PGA-603 |
| 文件页数： | 26/129页 |
| 文件大小： | 1528K |
| 代理商： | YF80532KC0211M |
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Datasheet
121
FERR#/PBE#
O
FERR#/PBE# (floating point error/pending break event) is a multiplexed signal and
its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/
PBE# indicates a floating-point error and will be asserted when the processor
detects an unmasked floating-point error. When STPCLK# is not asserted, FERR#/
PBE# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included
for compatibility with systems using MS-DOS*-type floating-point error reporting.
When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the
processor has a pending break event waiting for service. The assertion of FERR#/
PBE# indicates that the processor should be returned to the Normal state. When
FERR#/PBE# is asserted, indicating a break event, it will remain asserted until
STPCLK# is deasserted. For additional information on the pending break event
functionality, including the identification of support of the feature and enable/disable
information, refer to volume 3 of the Intel Architecture Software Developer's Manual
and the Intel Processor Identification and the CPUID Instruction application note.
This signal does not have on-die termination and must be terminated at the end
agent. See the appropriate platform design guideline for additional information.
GTLREF
I
GTLREF determines the signal reference level for AGTL+ input pins. GTLREF
should be set to either 2/3Vcc or 0.63*Vcc (future processors). GTLREF is used by
the AGTL+ receivers to determine if a signal is a logical 0 or a logical 1.
HIT#
HITM#
I/O
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation
results. Any system bus agent may assert both HIT# and HITM# together to
indicate that it requires a snoop stall, which can be continued by reasserting HIT#
and HITM# together.
Since multiple agents may deliver snoop results at the same time, HIT# and HITM#
are wire-OR signals which must connect the appropriate pins of all processor
system bus agents. In order to avoid wire-OR glitches associated with simultaneous
edge transitions driven by multiple drivers, HIT# and HITM# are activated on
specific clock edges and sampled on specific clock edges.
IERR#
O
IERR# (Internal Error) is asserted by a processor as the result of an internal error.
Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the
processor system bus. This transaction may optionally be converted to an external
error signal (e.g., NMI) by system core logic. The processor will keep IERR#
asserted until the assertion of RESET#.
This signal does not have on-die termination and must be terminated at the end
agent. See the appropriate platform design guideline for additional information.
IGNNE#
I
IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a
numeric error and continue to execute noncontrol floating-point instructions. If
IGNNE# is deasserted, the processor generates an exception on a noncontrol
floating-point instruction if a previous floating-point instruction caused an error.
IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O write bus transaction.
INIT#
I
INIT# (Initialization), when asserted, resets integer registers inside all processors
without affecting their internal caches or floating-point registers. Each processor
then begins execution at the power-on Reset vector configured during power-on
configuration. The processor continues to handle snoop requests during INIT#
assertion. INIT# is an asynchronous signal and must connect the appropriate pins
of all processor system bus agents.
If INIT# is sampled active on the active to inactive transition of RESET#, then the
processor executes its Built-in Self-Test (BIST).
Table 52. Signal Definitions (Sheet 5 of 10)
Name
Type
Description
相关PDF资料 |
PDF描述 |
|---|---|
| YF80532KC0412M | 2000 MHz, MICROPROCESSOR, CPGA603 |
| YF80532KC0371M | 1900 MHz, MICROPROCESSOR, CPGA603 |
| YG101-IC1 | SINGLE COLOR LED, YELLOW GREEN, 1.2 mm |
| YG104-IC1 | SINGLE COLOR LED, YELLOW GREEN, 1.2 mm |
| YG104-ICH | SINGLE COLOR LED, YELLOW GREEN, 1.2 mm |
相关代理商/技术参数 |
参数描述 |
|---|---|
| YFA014C049ZA | 制造商:Panasonic Industrial Company 功能描述:CHASSIS |
| YFA054C022ZA | 制造商:Panasonic Industrial Company 功能描述:COVER |
| YFAW025 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
| YFAW025-02 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
| YFAW025-03 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
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