- 您现在的位置：买卖IC网 > PDF目录48099 > YF80532KC0211M (INTEL CORP) 1500 MHz, MICROPROCESSOR, CPGA603 PDF资料下载
参数资料
| 型号： | YF80532KC0211M |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1500 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | MICRO, PGA-603 |
| 文件页数： | 72/129页 |
| 文件大小： | 1528K |
| 代理商： | YF80532KC0211M |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页当前第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页
Datasheet
47
System Bus Signal Quality Specifications
System Bus Signal Quality
Specifications
3
Source synchronous data transfer requires the clean reception of data signals and their associated
strobes. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage
swing will adversely affect system timings. Ringback and signal non-monotinicity cannot be
tolerated since these phenomena may inadvertently advance receiver state machines. Excessive
signal swings (overshoot and undershoot) are detrimental to silicon gate oxide integrity, and can
cause device failure if absolute voltage limits are exceeded. Additionally, overshoot and
undershoot can degrade timing due to the build up of inter-symbol interference (ISI) effects. For
these reasons, it is crucial that the designer assure acceptable signal quality across all systematic
variations encountered in volume manufacturing.
This section documents signal quality metrics used to derive topology and routing guidelines
through simulation and all specifications are specified at the processor core (pad measurements).
Specifications for signal quality are for measurements at the processor core only and are only
observable through simulation. The same is true for all system bus AC timing specifications in
3.1
System Bus Clock (BCLK) Signal Quality
Specifications and Measurement Guidelines
Table 22 describes the signal quality specifications at the processor pads for the processor system
bus clock (BCLK) signals. Figure 20 describes the signal quality waveform for the system bus
clock at the processor pads.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal can dip back to after passing the V
IH (rising) or VIL (falling) voltage limits. This
specification is an absolute value.
Table 22. BCLK Signal Quality Specifications
Parameter
Min
Max
Unit
Figure
Notes1
BCLK[1:0] Overshoot
N/A
0.30
V
BCLK[1:0] Undershoot
N/A
0.30
V
BCLK[1:0] Ringback Margin
0.20
N/A
V
BCLK[1:0] Threshold Region
N/A
0.10
V
2
相关PDF资料 |
PDF描述 |
|---|---|
| YF80532KC0412M | 2000 MHz, MICROPROCESSOR, CPGA603 |
| YF80532KC0371M | 1900 MHz, MICROPROCESSOR, CPGA603 |
| YG101-IC1 | SINGLE COLOR LED, YELLOW GREEN, 1.2 mm |
| YG104-IC1 | SINGLE COLOR LED, YELLOW GREEN, 1.2 mm |
| YG104-ICH | SINGLE COLOR LED, YELLOW GREEN, 1.2 mm |
相关代理商/技术参数 |
参数描述 |
|---|---|
| YFA014C049ZA | 制造商:Panasonic Industrial Company 功能描述:CHASSIS |
| YFA054C022ZA | 制造商:Panasonic Industrial Company 功能描述:COVER |
| YFAW025 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
| YFAW025-02 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
| YFAW025-03 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
发布紧急采购，3分钟左右您将得到回复。