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参数资料
| 型号： | YF80532KC0211M |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1500 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | MICRO, PGA-603 |
| 文件页数： | 29/129页 |
| 文件大小： | 1528K |
| 代理商： | YF80532KC0211M |
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124
Datasheet
SM_ALERT#
O
SM_ALERT# (SMBus Alert) is an asynchronous interrupt line associated with the
SMBus Thermal Sensor device. It is an open-drain output and the processor
includes a 10k
pull-up resistor to SM_VCC for this signal. It is only available on the
Intel Xeon processor in INT-mPGA package. For more information on the usage of
the SM_ALERT# pin, see Section 6.4.5.
SM_CLK
I/O
The SM_CLK (SMBus Clock) signal is an input clock to the system management
logic which is required for operation of the system management features of the Intel
Xeon processor MP on the 0.13 micron process processor. This clock is driven by
the SMBus controller and is asynchronous to other clocks in the processor.The
processor includes a 10 k
pull-up resistor to SM_VCC for this signal. It is only
available on the Intel Xeon processor in INT-mPGA package.
SM_DAT
I/O
The SM_DAT (SMBus Data) signal is the data signal for the SMBus. This signal
provides the single-bit mechanism for transferring data between SMBus
devices.The processor includes a 10 k
pull-up resistor to SM_VCC for this signal.
It is only available on the Intel Xeon processor in INT-mPGA package.
SM_EP_A[2:0]
I
The SM_EP_A (EEPROM Select Address) pins are decoded on the SMBus in
conjunction with the upper address bits in order to maintain unique addresses on
the SMBus in a system with multiple processors. To set an SM_EP_A line high, a
pull-up resistor should be used that is no larger than 1k
. The processor includes a
10k
pull-down resistor to VSS for each of these signals. It is only available on the
Intel Xeon processor in INT-mPGA package.
For more information on the usage of these pins, see Section 6.4.8.
SM_TS_A[1:0]
I
The SM_TS_A (Thermal Sensor Select Address) pins are decoded on the SMBus
in conjunction with the upper address bits in order to maintain unique addresses on
the SMBus in a system with multiple processors.
The device’s addressing, as implemented, includes a Hi-Z state for both address
pins. The use of the Hi-Z state is achieved by leaving the input floating
(unconnected). It is only available on the Intel Xeon processor in INT-mPGA
package.
For more information on the usage of these pins, see Section 6.4.8.
SM_VCC
I
Provides power to the SMBus components which are only available on the Intel
Xeon processor in INT-mPGA package. Additionally provides power for the VID and
BSEL logic. Intel Xeon processor MP on the 0.13 micron processprocessor
baseboards MUST provide SM_Vcc. See Figure for further details.
SM_WP
I
WP (Write Protect) can be used to write protect the Scratch EEPROM. The Scratch
EEPROM is write-protected when this input is pulled high to SM_VCC.The
processor includes a 10k pull-down resistor to VSS for this signal. It is only available
on the Intel Xeon processor in INT-mPGA package.
SMI#
I
SMI# (System Management Interrupt) is asserted asynchronously by system logic.
On accepting a System Management Interrupt, processors save the current state
and enter System Management Mode (SMM). An SMI Acknowledge transaction is
issued, and the processor begins program execution from the SMM handler.
If SMI# is asserted during the deassertion of RESET# the processor will tri-state its
outputs. It is only available on the Intel Xeon processor in INT-mPGA package.
STPCLK#
I
STPCLK# (Stop Clock), when asserted, causes processors to enter a low power
Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and
stops providing internal clock signals to all processor core units except the system
bus and APIC units. The processor continues to snoop bus transactions and
service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the
processor restarts its internal clock to all units and resumes execution. The
assertion of STPCLK# has no effect on the bus clock; STPCLK# is an
asynchronous input.
TCK
I
TCK (Test Clock) provides the clock input for the processor Test Bus (also known
as the Test Access Port).
Table 52. Signal Definitions (Sheet 8 of 10)
Name
Type
Description
相关PDF资料 |
PDF描述 |
|---|---|
| YF80532KC0412M | 2000 MHz, MICROPROCESSOR, CPGA603 |
| YF80532KC0371M | 1900 MHz, MICROPROCESSOR, CPGA603 |
| YG101-IC1 | SINGLE COLOR LED, YELLOW GREEN, 1.2 mm |
| YG104-IC1 | SINGLE COLOR LED, YELLOW GREEN, 1.2 mm |
| YG104-ICH | SINGLE COLOR LED, YELLOW GREEN, 1.2 mm |
相关代理商/技术参数 |
参数描述 |
|---|---|
| YFA014C049ZA | 制造商:Panasonic Industrial Company 功能描述:CHASSIS |
| YFA054C022ZA | 制造商:Panasonic Industrial Company 功能描述:COVER |
| YFAW025 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
| YFAW025-02 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
| YFAW025-03 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
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