参数资料
型号: YF80532KC0211M
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 1500 MHz, MICROPROCESSOR, CPGA603
封装: MICRO, PGA-603
文件页数: 30/129页
文件大小: 1528K
代理商: YF80532KC0211M
Datasheet
125
TDI
I
TDI (Test Data In) transfers serial test data into the processor. TDI provides the
serial input needed for JTAG specification support.
TDO
O
TDO (Test Data Out) transfers serial test data out of the processor. TDO provides
the serial output needed for JTAG specification support.
TESTHI[6:0]
I
All TESTHI[6:0] pins should be individually connected to VCC via a pull-up resistor
which matches the trace impedance within a range of ± 10 . TESTHI[3:0] and
TESTHI[6:5] may all be tied together and pulled up to VCC with a single resistor if
desired. However, utilization of boundary scan test will not be functional if these
pins are connected together. TESTHI4 must always be pulled up independently
from the other TESTHI pins. For optimum noise margin, all pull-up resistor values
used for TESTHI[6:0] pins should have a resistance value within ± 20% of the
impedance of the baseboard transmission line traces. For example, if the trace
impedance is 50
, then a value between 40 and 60 should be used.
THERMTRIP#
O
Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction
temperature has reached a level where permanent silicon damage may occur.
Measurement of the temperature is accomplished through an internal thermal
sensor which is configured to trip at approximately 135°C. Upon assertion of
THERMTRIP#, the processor will shut off its internal clocks (thus halting program
execution) in an attempt to reduce the processor junction temperature. To protect
the processor, its core voltage (Vcc) must be removed following the assertion of
THERMTRIP#. See Figure 15 and Table 18 for the appropriate power down
sequence and timing requirements.
Once activated, THERMTRIP# remains latched until RESET# is asserted. While
the assertion of the RESET# signal will de-assert THERMTRIP#, if the processor’s
junction temperature remains at or above the trip level, THERMTRIP# will again be
asserted.
This signal does not have on-die termination and must be terminated at the end
agent. See the appropriate platform design guideline for additional information.
TMS
I
TMS (Test Mode Select) is a JTAG specification support signal used by debug
tools.
This signal does not have on-die termination and must be terminated at the end
agent. See the appropriate platform design guideline for additional information.
TRDY#
I
TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive
a write or implicit writeback data transfer. TRDY# must connect the appropriate pins
of all system bus agents.
TRST#
I
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven
low during power on Reset. See the appropriate platform design guideline for
additional information.
VCCA
I
VCCA provides isolated power for the analog portion of the internal PLL’s. Use a
discrete RLC filter to provide clean power. Use the filter defined in Section 2.5 to
provide clean power to the PLL. The tolerance and total ESR for the filter is
important. Refer to the appropriate platform design guidelines for complete
implementation details.
VCCIOPLL
I
VCCIOPLL provides isolated power for digital portion of the internal PLL’s. Follow the
guidelines for VCCA (Section 2.5). Refer to the appropriate platform design
guidelines for complete implementation details.
Table 52. Signal Definitions (Sheet 9 of 10)
Name
Type
Description
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