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参数资料
| 型号： | YF80532KC0211M |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1500 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | MICRO, PGA-603 |
| 文件页数： | 13/129页 |
| 文件大小： | 1528K |
| 代理商： | YF80532KC0211M |
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Datasheet
11
Introduction
1
The Intel Xeon processor MP with up to 2-MB L3 cache on the 0.13 micron process is based on
the Intel NetBurstTM microarchitecture, which operates at significantly higher clock speeds and
delivers performance levels that are significantly higher than previous generations of IA-32
processors. While based on the Intel NetBurst microarchitecture, it maintains the tradition of
compatibility with IA-32 software. The Intel NetBurst microarchitecture features include Hyper
Pipelined Technology, a Rapid Execution Engine, a 400 MHz system bus, and an Execution Trace
Cache. The Hyper Pipelined Technology doubles the pipeline depth in the processor, allowing the
processor to reach much higher core frequencies. The Rapid Execution Engine allows the two
integer ALUs in the processor to run at twice the core frequency, which allows many integer
instructions to execute in one half of the internal core clock period. The 400 MHz system bus is a
quad-pumped bus running off a 100 MHz system bus clock making 3.2 GB/sec data transfer rates
possible. The Execution Trace Cache is a L1 cache that stores approximately twelve thousand
decoded micro-operations, which removes the decoder from the main execution path and increases
performance.
Improved features within the Intel NetBurst microarchitecture include Advanced Dynamic
Execution, Advanced Transfer Cache, enhanced floating point and multi-media unit, and
Streaming SIMD Extensions 2 (SSE2). The Advanced Dynamic Execution improves speculative
execution and branch prediction internal to the processor. The Advanced Transfer Cache is a
512-KB, on-die L2 cache with increased bandwidth over previous microarchitectures. The floating
point and multi-media units have been improved by making the registers 128 bits wide and adding
a separate register for data movement. Finally, SSE2 adds 144 new instructions for double-
precision floating point, SIMD integer, and memory management.
In addition, the Intel Xeon processor MP with up to 2-MB L3 cache includes Hyper-Threading
Technology. This new technology delivers two logical processors that can execute different tasks
simultaneously using shared hardware resources. As a result, multi-threaded applications will
execute on more than one thread per physical processor. This will increasing the performance of
system applications.
The Intel Xeon processors MP with up to 2-MB L3 Cache are intended for high performance server
systems with up to four processors on one bus. The processor is designed for 1-4 way (and beyond)
designs.
The Intel Xeon processor MP with up to 2-MB L3 cache is available with 1 MB or 2 MB of
integrated level 3 (L3) cache. All versions of this processor will include manageability features and
are based upon the Intel NetBurst microarchitecture. Components of the manageability features
include an OEM EEPROM and Processor Information ROM which are accessed through a SMBus
interface and contain information relevant to the particular processor and system in which it is
installed. In addition, enhancements have been made to the Machine Check Architecture.
The Intel Xeon processor MP with 400 MHz system bus support will be offered only in the
Interposer Micro-Pin Grid Array (INT-mPGA) package. These output pins can interface with a
thermal sensor device that is placed on the baseboard. The 603-pin socket will accommodate the
Intel Xeon processor in the INT-mPGA package. The different processor features are summarized
in Table 1.
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| YFAW025-02 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
| YFAW025-03 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:Pin Header : 2.5mm PITCH |
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